| /drivers/pinctrl/starfive/ |
| A D | pinctrl-starfive-jh7110-aon.c | 100 unsigned long mis; in jh7110_aon_irq_handler() local
105 mis = readl_relaxed(sfp->base + JH7110_AON_GPIOMIS); in jh7110_aon_irq_handler()
106 for_each_set_bit(pin, &mis, JH7110_AON_NGPIO) in jh7110_aon_irq_handler()
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| A D | pinctrl-starfive-jh7110-sys.c | 367 unsigned long mis; in jh7110_sys_irq_handler() local
372 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0); in jh7110_sys_irq_handler()
373 for_each_set_bit(pin, &mis, 32) in jh7110_sys_irq_handler()
376 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1); in jh7110_sys_irq_handler()
377 for_each_set_bit(pin, &mis, 32) in jh7110_sys_irq_handler()
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| A D | pinctrl-starfive-jh7100.c | 1179 unsigned long mis; in starfive_gpio_irq_handler() local
1184 mis = readl_relaxed(sfp->base + GPIOMIS + 0); in starfive_gpio_irq_handler()
1185 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
1188 mis = readl_relaxed(sfp->base + GPIOMIS + 4); in starfive_gpio_irq_handler()
1189 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
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| /drivers/clocksource/ |
| A D | timer-sp.h | 42 int mis; member
58 void __iomem *mis; member
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| /drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| A D | dce60_resource.c | 811 if (pool->base.mis[i] != NULL) { in dce60_resource_destruct()
812 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce60_resource_destruct()
813 pool->base.mis[i] = NULL; in dce60_resource_destruct()
1047 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce60_construct()
1048 if (pool->base.mis[i] == NULL) { in dce60_construct()
1245 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce61_construct()
1246 if (pool->base.mis[i] == NULL) { in dce61_construct()
1442 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce64_construct()
1443 if (pool->base.mis[i] == NULL) { in dce64_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| A D | dce80_resource.c | 817 if (pool->base.mis[i] != NULL) { in dce80_resource_destruct()
818 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce80_resource_destruct()
819 pool->base.mis[i] = NULL; in dce80_resource_destruct()
1057 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce80_construct()
1058 if (pool->base.mis[i] == NULL) { in dce80_construct()
1257 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce81_construct()
1258 if (pool->base.mis[i] == NULL) { in dce81_construct()
1454 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce83_construct()
1455 if (pool->base.mis[i] == NULL) { in dce83_construct()
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| /drivers/pinctrl/spear/ |
| A D | pinctrl-plgpio.c | 49 u32 mis; /* mask interrupt status register */ member
386 regmap_read(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
392 regmap_write(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
512 plgpio->regs.mis = val; in plgpio_probe_dt()
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| /drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| A D | dce100_resource.c | 770 if (pool->base.mis[i] != NULL) { in dce100_resource_destruct()
771 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce100_resource_destruct()
772 pool->base.mis[i] = NULL; in dce100_resource_destruct()
1092 pool->base.mis[i] = dce100_mem_input_create(ctx, i); in dce100_resource_construct()
1093 if (pool->base.mis[i] == NULL) { in dce100_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| A D | dce110_resource.c | 826 if (pool->base.mis[i] != NULL) { in dce110_resource_destruct()
827 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce110_resource_destruct()
828 pool->base.mis[i] = NULL; in dce110_resource_destruct()
1138 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
1272 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1453 pool->base.mis[i] = dce110_mem_input_create(ctx, i); in dce110_resource_construct()
1454 if (pool->base.mis[i] == NULL) { in dce110_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| A D | dce120_resource.c | 611 if (pool->base.mis[i] != NULL) { in dce120_resource_destruct()
612 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce120_resource_destruct()
613 pool->base.mis[i] = NULL; in dce120_resource_destruct()
1187 pool->base.mis[j] = dce120_mem_input_create(ctx, i); in dce120_resource_construct()
1189 if (pool->base.mis[j] == NULL) { in dce120_resource_construct()
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| /drivers/net/ethernet/realtek/rtase/ |
| A D | rtase_main.c | 214 u32 len = ring->mis.len[entry]; in rtase_tx_clear_range()
221 ring->mis.len[entry] = 0; in rtase_tx_clear_range()
285 rtase_unmap_tx_skb(tp->pdev, ring->mis.len[entry], desc); in tx_handler()
286 ring->mis.len[entry] = 0; in tx_handler()
333 ring->mis.len[i] = 0; in rtase_tx_desc_init()
412 &ring->mis.data_phy_addr[i]); in rtase_rx_ring_fill()
547 ring->mis.data_phy_addr[entry], in rx_handler()
601 ring->mis.data_phy_addr[i] = 0; in rtase_rx_desc_init()
1292 ring->mis.len[entry] = len; in rtase_xmit_frags()
1391 ring->mis.len[entry] = len; in rtase_start_xmit()
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| A D | rtase.h | 298 } mis; member
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| /drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| A D | dce112_resource.c | 791 if (pool->base.mis[i] != NULL) { in dce112_resource_destruct()
792 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce112_resource_destruct()
793 pool->base.mis[i] = NULL; in dce112_resource_destruct()
1340 pool->base.mis[i] = dce112_mem_input_create(ctx, i); in dce112_resource_construct()
1341 if (pool->base.mis[i] == NULL) { in dce112_resource_construct()
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| /drivers/media/dvb-frontends/ |
| A D | stv0900_core.c | 1544 enum fe_stv0900_demod_num demod, int mis) in stv0900_set_mis() argument
1548 if (mis < 0 || mis > 255) { in stv0900_set_mis()
1552 dprintk("Enable MIS filtering - %d\n", mis); in stv0900_set_mis()
1554 stv0900_write_reg(intp, ISIENTRY, mis); in stv0900_set_mis()
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| A D | stv090x.c | 3441 static int stv090x_set_mis(struct stv090x_state *state, int mis) in stv090x_set_mis() argument
3445 if (mis < 0 || mis > 255) { in stv090x_set_mis()
3452 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis); in stv090x_set_mis()
3457 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0) in stv090x_set_mis()
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| /drivers/crypto/stm32/ |
| A D | stm32-cryp.c | 168 u32 mis; member
2219 cryp->irq_status = stm32_cryp_read(cryp, cryp->caps->mis); in stm32_cryp_irq()
2506 .mis = UX500_CRYP_MIS,
2529 .mis = CRYP_MISR,
2552 .mis = CRYP_MISR,
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 244 struct mem_input *mis[MAX_PIPES]; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 1490 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1546 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
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| /drivers/clk/ |
| A D | Kconfig | 399 Adapter driver so that any PWM output can be (mis)used as clock signal
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 3686 pipe_ctx->plane_res.mi = pool->mis[id_src[i]]; in acquire_resource_from_hw_enabled_state()
3831 pipe_ctx->plane_res.mi = pool->mis[pipe_idx]; in acquire_otg_master_pipe_for_stream()
5455 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 536 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 1533 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 2849 free_pipe->plane_res.mi = pool->mis[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 1887 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
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| /drivers/hwmon/ |
| A D | Kconfig | 2303 the risk of mis-detecting SPD5118 compliant devices. However, it
|