Searched refs:mmHDP_MEM_POWER_CTRL (Results 1 – 3 of 3) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | hdp_v5_0.c | 54 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
82 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_0_update_mem_power_gating()
124 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_0_update_mem_power_gating()
190 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_get_clockgating_state()
|
| A D | hdp_v4_0.c | 32 #define mmHDP_MEM_POWER_CTRL 0x00d4 macro
102 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); in hdp_v4_0_update_clock_gating()
116 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); in hdp_v4_0_update_clock_gating()
|
| /drivers/gpu/drm/amd/include/asic_reg/hdp/ |
| A D | hdp_5_0_0_offset.h | 62 #define mmHDP_MEM_POWER_CTRL … macro
|
Completed in 6 milliseconds