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Searched refs:mmMAILBOX_INT_CNTL (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dmxgpu_vi.c504 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_vi_set_mailbox_ack_irq()
508 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_ack_irq()
537 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_vi_set_mailbox_rcv_irq()
541 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_rcv_irq()
A Dmxgpu_nv.c304 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_ack_irq()
311 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_nv_set_mailbox_ack_irq()
380 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_rcv_irq()
387 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_nv_set_mailbox_rcv_irq()
A Dmxgpu_nv.h91 #define mmMAILBOX_INT_CNTL 0xE5F macro
/drivers/gpu/drm/amd/include/asic_reg/bif/
A Dbif_5_0_d.h187 #define mmMAILBOX_INT_CNTL 0x14d1 macro
/drivers/gpu/drm/amd/include/asic_reg/nbif/
A Dnbif_6_1_offset.h1151 #define mmMAILBOX_INT_CNTL … macro
/drivers/gpu/drm/amd/include/asic_reg/nbio/
A Dnbio_7_4_offset.h2934 #define mmMAILBOX_INT_CNTL … macro
A Dnbio_7_0_offset.h4504 #define mmMAILBOX_INT_CNTL … macro

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