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Searched refs:mmPWR_DISP_TIMER2_CONTROL_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/smuio/
A Dsmuio_10_0_2_offset.h89 #define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX macro
A Dsmuio_11_0_0_offset.h501 #define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX macro

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