| /drivers/gpu/drm/amd/amdgpu/ |
| A D | sdma_v5_2.c | 80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
197 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_2_ring_get_wptr()
235 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), in sdma_v5_2_ring_set_wptr()
248 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), in sdma_v5_2_ring_set_wptr()
568 …WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wp… in sdma_v5_2_gfx_resume_instance()
573 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_2_gfx_resume_instance()
609 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume_instance()
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| A D | sdma_v2_4.c | 205 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v2_4_ring_get_wptr()
221 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); in sdma_v2_4_ring_set_wptr()
439 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
455 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); in sdma_v2_4_gfx_resume()
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| A D | cik_sdma.c | 181 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; in cik_sdma_ring_get_wptr()
195 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], in cik_sdma_ring_set_wptr()
464 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
480 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); in cik_sdma_gfx_resume()
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| A D | sdma_v5_0.c | 79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
357 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_get_wptr()
399 ring->me, mmSDMA0_GFX_RB_WPTR), in sdma_v5_0_ring_set_wptr()
719 …WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wp… in sdma_v5_0_gfx_resume_instance()
724 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_0_gfx_resume_instance()
761 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), in sdma_v5_0_gfx_resume_instance()
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| A D | sdma_v3_0.c | 369 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v3_0_ring_get_wptr()
396 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); in sdma_v3_0_ring_set_wptr()
716 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
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| A D | sdma_v4_0.c | 92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
683 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); in sdma_v4_0_ring_get_wptr()
726 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, in sdma_v4_0_ring_set_wptr()
1104 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); in sdma_v4_0_gfx_resume()
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| /drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| A D | sdma0_4_1_offset.h | 214 #define mmSDMA0_GFX_RB_WPTR … macro
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| A D | sdma0_4_0_offset.h | 218 #define mmSDMA0_GFX_RB_WPTR 0x0085 macro
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| A D | sdma0_4_2_2_offset.h | 218 #define mmSDMA0_GFX_RB_WPTR … macro
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| A D | sdma0_4_2_offset.h | 214 #define mmSDMA0_GFX_RB_WPTR … macro
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| /drivers/gpu/drm/amd/include/asic_reg/oss/ |
| A D | oss_2_4_d.h | 191 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
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| A D | oss_3_0_1_d.h | 218 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
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| A D | oss_2_0_d.h | 250 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
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| A D | oss_3_0_d.h | 343 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
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| /drivers/gpu/drm/amd/include/asic_reg/gc/ |
| A D | gc_10_1_0_offset.h | 212 #define mmSDMA0_GFX_RB_WPTR … macro
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| A D | gc_10_3_0_offset.h | 200 #define mmSDMA0_GFX_RB_WPTR … macro
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