| /drivers/gpu/drm/i915/display/ |
| A D | intel_dp.h | 141 u32 mode_clock, u32 mode_hdisplay,
152 int mode_clock, int mode_hdisplay,
166 u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
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| A D | intel_dp.c | 819 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) in intel_dp_mode_to_fec_clock() argument
910 intel_dp_mode_to_fec_clock(mode_clock); in bigjoiner_bw_max_bpp()
945 u32 mode_clock, u32 mode_hdisplay, in get_max_compressed_bpp_with_joiner() argument
962 u32 mode_clock, u32 mode_hdisplay, in intel_dp_dsc_get_max_compressed_bpp() argument
987 (intel_dp_mode_to_fec_clock(mode_clock) * 8); in intel_dp_dsc_get_max_compressed_bpp()
1006 intel_dp_mode_to_fec_clock(mode_clock)); in intel_dp_dsc_get_max_compressed_bpp()
1018 int mode_clock, int mode_hdisplay, in intel_dp_dsc_get_slice_count() argument
1025 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) in intel_dp_dsc_get_slice_count()
1026 min_slice_count = DIV_ROUND_UP(mode_clock, in intel_dp_dsc_get_slice_count()
1029 min_slice_count = DIV_ROUND_UP(mode_clock, in intel_dp_dsc_get_slice_count()
[all …]
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| A D | intel_sdvo.c | 834 int mode_clock; in intel_sdvo_get_dtd_from_mode() local
851 mode_clock = mode->clock; in intel_sdvo_get_dtd_from_mode()
852 mode_clock /= 10; in intel_sdvo_get_dtd_from_mode()
853 dtd->part1.clock = mode_clock; in intel_sdvo_get_dtd_from_mode()
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| /drivers/gpu/drm/xlnx/ |
| A D | zynqmp_disp.c | 1327 unsigned long mode_clock) in zynqmp_disp_setup_clock() argument
1333 ret = clk_set_rate(disp->dpsub->vid_clk, mode_clock); in zynqmp_disp_setup_clock()
1340 diff = rate - mode_clock; in zynqmp_disp_setup_clock()
1341 if (abs(diff) > mode_clock / 20) in zynqmp_disp_setup_clock()
1344 mode_clock, rate); in zynqmp_disp_setup_clock()
1348 mode_clock, rate); in zynqmp_disp_setup_clock()
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| A D | zynqmp_disp.h | 48 unsigned long mode_clock);
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| /drivers/gpu/drm/arm/ |
| A D | hdlcd_drv.c | 214 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000; in hdlcd_show_pxlclock() local
217 seq_printf(m, "mode: %lu\n", mode_clock); in hdlcd_show_pxlclock()
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| /drivers/gpu/drm/renesas/rcar-du/ |
| A D | rcar_du_crtc.c | 210 unsigned long mode_clock = mode->clock * 1000; in rcar_du_crtc_set_display_timing() local
216 unsigned long target = mode_clock; in rcar_du_crtc_set_display_timing()
256 rcar_du_escr_divider(rcrtc->clock, mode_clock, in rcar_du_crtc_set_display_timing()
259 rcar_du_escr_divider(rcrtc->extclock, mode_clock, in rcar_du_crtc_set_display_timing()
263 mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext", in rcar_du_crtc_set_display_timing()
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| /drivers/gpu/drm/renesas/rz-du/ |
| A D | rzg2l_du_crtc.c | 67 unsigned long mode_clock = mode->clock * 1000; in rzg2l_du_crtc_set_display_timing() local
72 clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock); in rzg2l_du_crtc_set_display_timing()
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| /drivers/gpu/drm/tiny/ |
| A D | arcpgu.c | 345 unsigned long mode_clock = arcpgu->pipe.crtc.mode.crtc_clock * 1000; in arcpgu_show_pxlclock() local
348 seq_printf(m, "mode: %lu\n", mode_clock); in arcpgu_show_pxlclock()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_connectors.c | 106 unsigned int mode_clock, max_tmds_clock; in amdgpu_connector_get_monitor_bpc() local
169 mode_clock = amdgpu_connector->pixelclock_for_modeset; in amdgpu_connector_get_monitor_bpc()
175 connector->name, mode_clock, max_tmds_clock); in amdgpu_connector_get_monitor_bpc()
178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { in amdgpu_connector_get_monitor_bpc()
180 (mode_clock * 5/4 <= max_tmds_clock)) in amdgpu_connector_get_monitor_bpc()
189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { in amdgpu_connector_get_monitor_bpc()
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| /drivers/gpu/drm/bridge/ |
| A D | chipone-icn6211.c | 254 unsigned int mode_clock = mode->clock * 1000; in chipone_configure_pll() local
300 m = mode_clock / freq_s; in chipone_configure_pll()
314 delta = abs(mode_clock - freq_out); in chipone_configure_pll()
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| A D | ti-sn65dsi83.c | 329 int mode_clock = mode->clock; in sn65dsi83_get_lvds_range() local
332 mode_clock /= 2; in sn65dsi83_get_lvds_range()
334 return (mode_clock - 12500) / 25000; in sn65dsi83_get_lvds_range()
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| /drivers/gpu/drm/radeon/ |
| A D | radeon_connectors.c | 106 int mode_clock, max_tmds_clock; in radeon_get_monitor_bpc() local
176 mode_clock = radeon_connector->pixelclock_for_modeset; in radeon_get_monitor_bpc()
182 connector->name, mode_clock, max_tmds_clock); in radeon_get_monitor_bpc()
185 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { in radeon_get_monitor_bpc()
187 (mode_clock * 5/4 <= max_tmds_clock)) in radeon_get_monitor_bpc()
196 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { in radeon_get_monitor_bpc()
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| /drivers/gpu/drm/bridge/cadence/ |
| A D | cdns-dsi-core.c | 582 int mode_clock = (mode_valid_check ? mode->clock : mode->crtc_clock); in cdns_dsi_check_conf() local
589 ret = phy_mipi_dphy_get_default_config(mode_clock * 1000, in cdns_dsi_check_conf()
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