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Searched refs:mode_lib (Results 1 – 25 of 53) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_mode_vba_20.c238 mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth, in dml20_recalculate()
2055 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2369 if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) { in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2397 mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2608 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3401 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml20_ModeSupportAndSystemConfigurationFull()
4799 …+ mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mod… in dml20_ModeSupportAndSystemConfigurationFull()
5097 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel]; in dml20_ModeSupportAndSystemConfigurationFull()
5098 mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; in dml20_ModeSupportAndSystemConfigurationFull()
5099 mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel]; in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddisplay_mode_vba_20v2.c262 mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth, in dml20v2_recalculate()
2091 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2126 …mode_lib->vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDela… in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2128 …mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->v… in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2129 …mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPix… in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2431 mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2681 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3508 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml20v2_ModeSupportAndSystemConfigurationFull()
5213 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel]; in dml20v2_ModeSupportAndSystemConfigurationFull()
5214 mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddisplay_rq_dlg_calc_20.c39 struct display_mode_lib *mode_lib,
396 mode_lib->ip.pde_proc_buffer_size_64k_reqs; in get_meta_and_pte_attr()
715 get_meta_and_pte_attr(mode_lib, in get_surf_rq_param()
739 get_surf_rq_param(mode_lib, in dml20_rq_dlg_get_rq_params()
748 get_surf_rq_param(mode_lib, in dml20_rq_dlg_get_rq_params()
758 print__rq_params_st(mode_lib, rq_param); in dml20_rq_dlg_get_rq_params()
771 print__rq_regs_st(mode_lib, rq_regs); in dml20_rq_dlg_get_rq_reg()
1084 + mode_lib->soc.urgent_latency_us, in dml20_rq_dlg_get_dlg_params()
1344 calculate_ttu_cursor(mode_lib, in dml20_rq_dlg_get_dlg_params()
1360 calculate_ttu_cursor(mode_lib, in dml20_rq_dlg_get_dlg_params()
[all …]
A Ddisplay_rq_dlg_calc_20v2.c39 struct display_mode_lib *mode_lib,
396 mode_lib->ip.pde_proc_buffer_size_64k_reqs; in get_meta_and_pte_attr()
715 get_meta_and_pte_attr(mode_lib, in get_surf_rq_param()
739 get_surf_rq_param(mode_lib, in dml20v2_rq_dlg_get_rq_params()
748 get_surf_rq_param(mode_lib, in dml20v2_rq_dlg_get_rq_params()
758 print__rq_params_st(mode_lib, rq_param); in dml20v2_rq_dlg_get_rq_params()
771 print__rq_regs_st(mode_lib, rq_regs); in dml20v2_rq_dlg_get_rq_reg()
1085 + mode_lib->soc.urgent_latency_us, in dml20v2_rq_dlg_get_dlg_params()
1345 calculate_ttu_cursor(mode_lib, in dml20v2_rq_dlg_get_dlg_params()
1361 calculate_ttu_cursor(mode_lib, in dml20v2_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.c58 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in dml_get_voltage_level()
63 mode_lib->vba.soc = mode_lib->soc; in dml_get_voltage_level()
64 mode_lib->vba.ip = mode_lib->ip; in dml_get_voltage_level()
69 mode_lib->funcs.recalculate(mode_lib); in dml_get_voltage_level()
76 mode_lib->funcs.validate(mode_lib); in dml_get_voltage_level()
963 if (memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0 in recalculate_params()
964 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in recalculate_params()
970 mode_lib->vba.soc = mode_lib->soc; in recalculate_params()
971 mode_lib->vba.ip = mode_lib->ip; in recalculate_params()
974 mode_lib->funcs.recalculate(mode_lib); in recalculate_params()
[all …]
A Ddisplay_mode_lib.c161 struct display_mode_lib *mode_lib, in dml_log_pipe_params() argument
287 void dml_log_mode_support_params(struct display_mode_lib *mode_lib) in dml_log_mode_support_params() argument
291 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { in dml_log_mode_support_params()
298 … : [%s, %s]\n", mode_lib->vba.ViewportSizeSupport[i][0] ? "Supported" : "NOT S… in dml_log_mode_support_params()
304 … Buffer : [%s, %s]\n", mode_lib->vba.ROBSupport[i][0] ? "Supported" : "NOT Suppor… in dml_log_mode_support_params()
305 …K : [%s, %s]\n", mode_lib->vba.DISPCLK_DPPCLK_Support[i][0] ? "Supported" : "NOT … in dml_log_mode_support_params()
311 … : [%s, %s]\n", mode_lib->vba.PrefetchSupported[i][0] ? "Supported" : "NOT Su… in dml_log_mode_support_params()
312 … : [%s, %s]\n", mode_lib->vba.DynamicMetadataSupported[i][0] ? "Supported" : "NOT… in dml_log_mode_support_params()
315 …t Exceeded : [%s, %s]\n", mode_lib->vba.PTEBufferSizeNotExceeded[i][0] ? "Supported" : "NOT… in dml_log_mode_support_params()
317 …dml_print("DML SUPPORT: HostVMEnable : %d\n", mode_lib->vba.HostVMEnabl… in dml_log_mode_support_params()
[all …]
A Ddisplay_rq_dlg_helpers.h34 void print__rq_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_params…
35 void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_displ…
36 void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_…
37 void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display…
38 void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_…
40 void print__data_rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_r…
41 void print__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st …
42 void print__dlg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_s…
43 void print__ttu_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_ttu_regs_s…
A Ddisplay_rq_dlg_helpers.c29 void print__rq_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_params… in print__rq_params_st() argument
34 print__data_rq_sizing_params_st(mode_lib, &rq_param->sizing.rq_l); in print__rq_params_st()
36 print__data_rq_sizing_params_st(mode_lib, &rq_param->sizing.rq_c); in print__rq_params_st()
39 print__data_rq_dlg_params_st(mode_lib, &rq_param->dlg.rq_l); in print__rq_params_st()
41 print__data_rq_dlg_params_st(mode_lib, &rq_param->dlg.rq_c); in print__rq_params_st()
44 print__data_rq_misc_params_st(mode_lib, &rq_param->misc.rq_l); in print__rq_params_st()
46 print__data_rq_misc_params_st(mode_lib, &rq_param->misc.rq_c); in print__rq_params_st()
164 void print__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st … in print__rq_regs_st() argument
169 print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_l); in print__rq_regs_st()
171 print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_c); in print__rq_regs_st()
[all …]
A Ddisplay_mode_lib.h52 struct display_mode_lib *mode_lib,
64 struct display_mode_lib *mode_lib,
70 struct display_mode_lib *mode_lib,
77 struct display_mode_lib *mode_lib,
81 void (*recalculate)(struct display_mode_lib *mode_lib);
82 void (*validate)(struct display_mode_lib *mode_lib);
104 struct display_mode_lib *mode_lib,
108 void dml_log_mode_support_params(struct display_mode_lib *mode_lib);
A Ddml1_display_rq_dlg_calc.c927 mode_lib, in get_surf_rq_param()
970 mode_lib, in dml1_rq_dlg_get_rq_params()
980 mode_lib, in dml1_rq_dlg_get_rq_params()
1371 mode_lib, in dml1_rq_dlg_get_dlg_params()
1498 mode_lib, in dml1_rq_dlg_get_dlg_params()
1507 mode_lib, in dml1_rq_dlg_get_dlg_params()
1653 mode_lib, in dml1_rq_dlg_get_dlg_params()
1663 mode_lib, in dml1_rq_dlg_get_dlg_params()
1694 mode_lib, in dml1_rq_dlg_get_dlg_params()
1743 mode_lib, in dml1_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_mode_vba_32.c207 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
573 mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + mode_lib->vba.DPPPerPlane[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
672 …mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0]… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1545 mode_lib->vba.HTotal, mode_lib->vba.VTotal, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1834 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml32_ModeSupportAndSystemConfigurationFull()
1836 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] in dml32_ModeSupportAndSystemConfigurationFull()
1906 mode_lib->vba.htaps[k], mode_lib->vba.HTAPsChroma[k], mode_lib->vba.vtaps[k], in dml32_ModeSupportAndSystemConfigurationFull()
2646 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml32_ModeSupportAndSystemConfigurationFull()
3733 mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; in dml32_ModeSupportAndSystemConfigurationFull()
3735 mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddisplay_rq_dlg_calc_32.c44 struct display_mode_lib *mode_lib, in dml32_rq_dlg_get_rq_reg() argument
131 pte_row_height_linear = get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes, in dml32_rq_dlg_get_rq_reg()
163 stored_swath_l_bytes = get_det_stored_buffer_size_l_bytes(mode_lib, e2e_pipe_param, num_pipes, in dml32_rq_dlg_get_rq_reg()
165 stored_swath_c_bytes = get_det_stored_buffer_size_c_bytes(mode_lib, e2e_pipe_param, num_pipes, in dml32_rq_dlg_get_rq_reg()
167 is_phantom_pipe = get_is_phantom_pipe(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml32_rq_dlg_get_rq_reg()
202 print__rq_regs_st(mode_lib, rq_regs); in dml32_rq_dlg_get_rq_reg()
206 void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, in dml32_rq_dlg_get_dlg_reg() argument
288 vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, in dml32_rq_dlg_get_dlg_reg()
429 refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, in dml32_rq_dlg_get_dlg_reg()
611 print__ttu_regs_st(mode_lib, ttu_regs); in dml32_rq_dlg_get_dlg_reg()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_mode_vba_21.c1750 mode_lib, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2101 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2416 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2562 if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2614 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3635 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml21_ModeSupportAndSystemConfigurationFull()
3637 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0; in dml21_ModeSupportAndSystemConfigurationFull()
5220 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel]; in dml21_ModeSupportAndSystemConfigurationFull()
5221 mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; in dml21_ModeSupportAndSystemConfigurationFull()
5222 mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel]; in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddisplay_rq_dlg_calc_21.c755 mode_lib, in get_surf_rq_param()
782 mode_lib, in dml_rq_dlg_get_rq_params()
1140 mode_lib, in dml_rq_dlg_get_dlg_params()
1145 mode_lib, in dml_rq_dlg_get_dlg_params()
1255 mode_lib, in dml_rq_dlg_get_dlg_params()
1267 mode_lib, in dml_rq_dlg_get_dlg_params()
1337 mode_lib, in dml_rq_dlg_get_dlg_params()
1348 mode_lib, in dml_rq_dlg_get_dlg_params()
1656 mode_lib, in dml21_rq_dlg_get_dlg_reg()
1664 mode_lib, in dml21_rq_dlg_get_dlg_reg()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddisplay_mode_core.c6532 …mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][… in dml_prefetch_check()
6534 …mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][… in dml_prefetch_check()
6536 …mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][… in dml_prefetch_check()
7242 …mode_lib->ms.support.DISPCLK_DPPCLK_Support[j] = !((mode_lib->ms.RequiredDISPCLK[j] > mode_lib->ms… in dml_core_mode_support()
7793 mode_lib->mp.UrgentLatency = mode_lib->ms.UrgLatency; in dml_core_mode_support()
8240 mode_lib->ms.DCFCLK = mode_lib->ms.DCFCLKState[mode_lib->ms.support.MaximumMPCCombine]; in dml_core_mode_support()
8241 mode_lib->ms.ReturnBW = mode_lib->ms.ReturnBWPerState[mode_lib->ms.support.MaximumMPCCombine]; in dml_core_mode_support()
8242 …mode_lib->ms.ReturnDRAMBW = mode_lib->ms.ReturnDRAMBWPerState[mode_lib->ms.support.MaximumMPCComb… in dml_core_mode_support()
10057 mode_lib->ms.soc = mode_lib->soc; in cache_ip_soc_cfg()
10058 mode_lib->ms.ip = mode_lib->ip; in cache_ip_soc_cfg()
[all …]
A Ddml_display_rq_dlg_calc.c40 struct display_mode_lib_st *mode_lib, in dml_rq_dlg_get_rq_reg() argument
43 dml_uint_t plane_idx = dml_get_plane_idx(mode_lib, pipe_idx); in dml_rq_dlg_get_rq_reg()
159 is_phantom_pipe = dml_get_is_phantom_pipe(mode_lib, pipe_idx); in dml_rq_dlg_get_rq_reg()
199 struct display_mode_lib_st *mode_lib, in dml_rq_dlg_get_dlg_reg() argument
202 dml_uint_t plane_idx = dml_get_plane_idx(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
299 if (dml_get_plane_idx(mode_lib, i) == plane_idx) { in dml_rq_dlg_get_dlg_reg()
322 min_ttu_vblank = dml_get_min_ttu_vblank_in_us(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
340 dst_y_prefetch = dml_get_dst_y_prefetch(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
343 dst_y_per_vm_flip = dml_get_dst_y_per_vm_flip(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
362 vratio_pre_l = dml_get_vratio_prefetch_l(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_mode_util.c354 void dml_print_mode_support(struct display_mode_lib_st *mode_lib, dml_uint_t j) in dml_print_mode_support() argument
358 …dml_print("DML: MODE SUPPORT: Mode Supported : %s\n", mode_lib->ms.support.ModeSu… in dml_print_mode_support()
370 …dml_print("DML: MODE SUPPORT: P2IWith420 : %s\n", mode_lib->ms… in dml_print_mode_support()
385 …dml_print("DML: MODE SUPPORT: ROB Support : %s\n", mode_lib->ms… in dml_print_mode_support()
393 …dml_print("DML: MODE SUPPORT: Pitch Support : %s\n", mode_lib->ms… in dml_print_mode_support()
404 …((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !mode_lib->scratch.dml_core_mode_s… in dml_print_mode_support()
407 …raining Support : %s\n", (!mode_lib->ms.policy.USRRetrainingRequiredFinal || &… in dml_print_mode_support()
757 dml_uint_t dml_get_plane_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx) in dml_get_plane_idx() argument
759 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_plane_idx()
763 dml_uint_t dml_get_pipe_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t plane_idx) in dml_get_pipe_idx() argument
[all …]
A Ddisplay_mode_core.h33 dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib);
34 void dml_core_mode_support_partial(struct display_mode_lib_st *mode_lib);
35 void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struct dml_clk_cfg_st *c…
40 const struct display_mode_lib_st *mode_lib,
65 struct display_mode_lib_st *mode_lib,
70 struct display_mode_lib_st *mode_lib,
78 dml_bool_t dml_get_is_phantom_pipe(struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx);
80 …ecl(variable, type) type dml_get_##variable(struct display_mode_lib_st *mode_lib, dml_uint_t surfa…
81 #define dml_get_var_decl(var, type) type dml_get_##var(struct display_mode_lib_st *mode_lib)
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4_calcs.c7291 mode_lib->ms.TimeCalc = 24 / mode_lib->ms.dcfclk_deepsleep; in dml_core_ms_prefetch_check()
8576 …mode_lib->ms.RequiredDPPCLK[k] = mode_lib->ms.MinDPPCLKUsingSingleDPP[k] / mode_lib->ms.NoOfDPP[k]; in dml_core_mode_support()
8577 mode_lib->ms.GlobalDPPCLK = math_max2(mode_lib->ms.GlobalDPPCLK, mode_lib->ms.RequiredDPPCLK[k]); in dml_core_mode_support()
8580 …mode_lib->ms.support.DISPCLK_DPPCLK_Support = !((mode_lib->ms.RequiredDISPCLK > mode_lib->ms.max_d… in dml_core_mode_support()
9067 mode_lib->ms.TripToMemory = math_max2(mode_lib->ms.UrgLatency, mode_lib->ms.TripToMemory); in dml_core_mode_support()
9557 mode_lib->ms.support.ODMMode[k] = mode_lib->ms.ODMMode[k]; in dml_core_mode_support()
10940 mode_lib->mp.TCalc = 24.0 / mode_lib->mp.DCFCLKDeepSleep; in dml_core_mode_programming()
11025 mode_lib->mp.TripToMemory = math_max2(mode_lib->mp.UrgentLatency, mode_lib->mp.TripToMemory); in dml_core_mode_programming()
11829 mode_lib->mp.MinTTUVBlank[k] = mode_lib->mp.TWait[k] + mode_lib->mp.ExtraLatency; in dml_core_mode_programming()
11831 mode_lib->mp.MinTTUVBlank[k] = mode_lib->mp.TCalc + mode_lib->mp.MinTTUVBlank[k]; in dml_core_mode_programming()
[all …]
A Ddml2_core_dcn4_calcs.h21 …lay_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchu…
22 …lay_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_disp…
23 …play_cfg *dml2_display_cfg, struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchu…
24 …et_stream_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_per_…
25 …obal_sync_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, union dml2_globa…
26 …get_mcache_allocation(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_mcac…
27 …lay_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_plan…
28 void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mode_lib *mode_lib, st…
29 …lay_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_stre…
30 void dml2_core_calcs_get_mall_allocation(struct dml2_core_internal_display_mode_lib *mode_lib, unsi…
[all …]
A Ddml2_core_dcn4.c145 patch_ip_params_with_ip_caps(&core->clean_me_up.mode_lib.ip, in_out->ip_caps); in core_dcn4_initialize()
146 core->clean_me_up.mode_lib.ip.imall_supported = false; in core_dcn4_initialize()
149 memcpy(&core->clean_me_up.mode_lib.soc, in_out->soc_bb, sizeof(struct dml2_soc_bb)); in core_dcn4_initialize()
351 dml2_core_calcs_get_stream_fams2_programming(&core->clean_me_up.mode_lib, in pack_mode_programming_params_with_implicit_subvp()
420 l->mode_support_ex_params.mode_lib = &core->clean_me_up.mode_lib; in core_dcn4_mode_support()
556 l->mode_programming_ex_params.mode_lib = &core->clean_me_up.mode_lib; in core_dcn4_mode_programming()
562 &core->clean_me_up.mode_lib.soc); in core_dcn4_mode_programming()
588 …if (core->clean_me_up.mode_lib.mp.MaxActiveDRAMClockChangeLatencySupported[plane_index] >= core->c… in core_dcn4_mode_programming()
590 …else if (core->clean_me_up.mode_lib.mp.TWait[plane_index] >= core->clean_me_up.mode_lib.soc.power_… in core_dcn4_mode_programming()
634 struct dml2_core_internal_display_mode_lib *mode_lib = &in_out->instance->clean_me_up.mode_lib; in core_dcn4_populate_informative() local
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_rq_dlg_calc_30.c342 …(is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_p… in get_meta_and_pte_attr()
343 …: (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chro… in get_meta_and_pte_attr()
727 get_meta_and_pte_attr(mode_lib, in get_surf_rq_param()
758 get_surf_rq_param(mode_lib, in dml_rq_dlg_get_rq_params()
768 get_surf_rq_param(mode_lib, in dml_rq_dlg_get_rq_params()
779 print__rq_params_st(mode_lib, rq_param); in dml_rq_dlg_get_rq_params()
792 print__rq_regs_st(mode_lib, rq_regs); in dml30_rq_dlg_get_rq_reg()
1515 calculate_ttu_cursor(mode_lib, in dml_rq_dlg_get_dlg_params()
1531 calculate_ttu_cursor(mode_lib, in dml_rq_dlg_get_dlg_params()
1722 print__ttu_regs_st(mode_lib, disp_ttu_regs); in dml_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_rq_dlg_calc_31.c725 mode_lib, in get_surf_rq_param()
1202 mode_lib, in dml_rq_dlg_get_dlg_params()
1214 mode_lib, in dml_rq_dlg_get_dlg_params()
1240 mode_lib, in dml_rq_dlg_get_dlg_params()
1252 mode_lib, in dml_rq_dlg_get_dlg_params()
1287 mode_lib, in dml_rq_dlg_get_dlg_params()
1299 mode_lib, in dml_rq_dlg_get_dlg_params()
1325 mode_lib, in dml_rq_dlg_get_dlg_params()
1336 mode_lib, in dml_rq_dlg_get_dlg_params()
1369 mode_lib, in dml_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_rq_dlg_calc_314.c812 mode_lib, in get_surf_rq_param()
1290 mode_lib, in dml_rq_dlg_get_dlg_params()
1302 mode_lib, in dml_rq_dlg_get_dlg_params()
1328 mode_lib, in dml_rq_dlg_get_dlg_params()
1340 mode_lib, in dml_rq_dlg_get_dlg_params()
1375 mode_lib, in dml_rq_dlg_get_dlg_params()
1387 mode_lib, in dml_rq_dlg_get_dlg_params()
1413 mode_lib, in dml_rq_dlg_get_dlg_params()
1424 mode_lib, in dml_rq_dlg_get_dlg_params()
1457 mode_lib, in dml_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c745 const struct dml2_core_internal_display_mode_lib *mode_lib = &in_out->core->clean_me_up.mode_lib; in dpmm_dcn4_map_watermarks() local
753 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_exit = (int unsigned)(mode_lib->mp.Watermark… in dpmm_dcn4_map_watermarks()
758 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].urgent = (int unsigned)(mode_lib->mp.Watermark.… in dpmm_dcn4_map_watermarks()
759 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].usr = (int unsigned)(mode_lib->mp.Watermark.USR… in dpmm_dcn4_map_watermarks()
763 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_nom = (unsigned int)(mode_lib->mp.F… in dpmm_dcn4_map_watermarks()
764 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_mall = (unsigned int)(mode_lib->mp.… in dpmm_dcn4_map_watermarks()
769 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_B].sr_exit = (int unsigned)(mode_lib->mp.Watermark… in dpmm_dcn4_map_watermarks()
774 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_B].urgent = (int unsigned)(mode_lib->mp.Watermark.… in dpmm_dcn4_map_watermarks()
775 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_B].usr = (int unsigned)(mode_lib->mp.Watermark.USR… in dpmm_dcn4_map_watermarks()
779 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_B].frac_urg_bw_nom = (unsigned int)(mode_lib->mp.F… in dpmm_dcn4_map_watermarks()
[all …]

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