Home
last modified time | relevance | path

Searched refs:mode_reg (Results 1 – 25 of 55) sorted by relevance

123

/drivers/clk/qcom/
A Dclk-pll.c31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
71 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
76 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); in clk_pll_disable()
153 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); in clk_pll_set_rate()
250 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8); in clk_pll_configure_sr()
259 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0); in clk_pll_configure_sr_hpm_lp()
269 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); in clk_pll_sr2_enable()
[all …]
A Dclk-hfpll.c67 regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); in __clk_hfpll_enable()
76 regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); in __clk_hfpll_enable()
91 regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); in __clk_hfpll_enable()
104 regmap_read(regmap, hd->mode_reg, &mode); in clk_hfpll_enable()
121 regmap_update_bits(regmap, hd->mode_reg, in __clk_hfpll_disable()
213 regmap_read(regmap, hd->mode_reg, &mode); in clk_hfpll_init()
239 regmap_read(regmap, hd->mode_reg, &mode); in hfpll_is_enabled()
A Dhfpll.c18 .mode_reg = 0x00,
36 .mode_reg = 0x00,
53 .mode_reg = 0x00,
70 .mode_reg = 0x00,
A Dclk-hfpll.h11 u32 mode_reg; member
A Dclk-pll.h44 u32 mode_reg; member
/drivers/regulator/
A Dsy8824x.c22 unsigned int mode_reg; member
45 regmap_update_bits(rdev->regmap, cfg->mode_reg, in sy8824_set_mode()
49 regmap_update_bits(rdev->regmap, cfg->mode_reg, in sy8824_set_mode()
65 ret = regmap_read(rdev->regmap, cfg->mode_reg, &val); in sy8824_get_mode()
168 .mode_reg = 0x00,
178 .mode_reg = 0x00,
188 .mode_reg = 0x01,
198 .mode_reg = 0x01,
A Dpca9450-regulator.c30 unsigned int mode_reg; /* ctrl */ member
329 dvs->mode_reg, dvs->mode_mask, val); in pca9450_buck_set_mode()
385 .mode_reg = PCA9450_REG_BUCK1CTRL,
418 .mode_reg = PCA9450_REG_BUCK2CTRL,
451 .mode_reg = PCA9450_REG_BUCK3CTRL,
475 .mode_reg = PCA9450_REG_BUCK4CTRL,
499 .mode_reg = PCA9450_REG_BUCK5CTRL,
523 .mode_reg = PCA9450_REG_BUCK6CTRL,
653 .mode_reg = PCA9450_REG_BUCK1CTRL,
686 .mode_reg = PCA9450_REG_BUCK2CTRL,
[all …]
A Dfan53555.c141 unsigned int mode_reg; member
197 regmap_update_bits(rdev->regmap, di->mode_reg, in fan53555_set_mode()
215 ret = regmap_read(rdev->regmap, di->mode_reg, &val); in fan53555_get_mode()
515 di->mode_reg = FAN53555_CONTROL; in fan53555_device_setup()
529 di->mode_reg = di->vol_reg; in fan53555_device_setup()
537 di->mode_reg = FAN53555_VSEL1; in fan53555_device_setup()
540 di->mode_reg = FAN53555_VSEL0; in fan53555_device_setup()
545 di->mode_reg = TCS4525_COMMAND; in fan53555_device_setup()
A Drtq2134-regulator.c66 unsigned int mode_reg; member
91 return regmap_update_bits(rdev->regmap, desc->mode_reg, desc->mode_mask, in rtq2134_buck_set_mode()
102 ret = regmap_read(rdev->regmap, desc->mode_reg, &mode); in rtq2134_buck_get_mode()
296 .mode_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG0, \
A Dmt6360-regulator.c37 unsigned int mode_reg; member
243 ret = regmap_update_bits(regmap, rdesc->mode_reg, rdesc->mode_mask, val << shift); in mt6360_regulator_set_mode()
260 ret = regmap_read(regmap, rdesc->mode_reg, &val); in mt6360_regulator_get_mode()
345 .mode_reg = mreg, \
A Dpv88080-regulator.c34 unsigned int mode_reg; member
201 ret = regmap_read(rdev->regmap, info->mode_reg, &data); in pv88080_buck_get_mode()
242 return regmap_update_bits(rdev->regmap, info->mode_reg, in pv88080_buck_set_mode()
445 pv88080_regulator_info[i].mode_reg in pv88080_i2c_probe()
A Drtq2208-regulator.c93 unsigned int mode_reg; member
125 return regmap_update_bits(rdev->regmap, rdesc->mode_reg, in rtq2208_set_mode()
136 ret = regmap_read(rdev->regmap, rdesc->mode_reg, &mode_val); in rtq2208_get_mode()
434 rdesc->mode_reg = BUCK_RG_SHIFT(curr_info->base, 2); in rtq2208_init_regulator_desc()
A Dab8500.c190 u8 mode_reg; member
414 reg = info->mode_reg; in ab8500_regulator_set_mode()
512 info->mode_bank, info->mode_reg, &val); in ab8500_regulator_get_mode()
1077 .mode_reg = 0x54,
1098 .mode_reg = 0x54,
/drivers/net/can/ctucanfd/
A Dctucanfd_base.c331 (mode_reg | REG_MODE_ILBP) : in ctucan_set_mode()
332 (mode_reg & ~REG_MODE_ILBP); in ctucan_set_mode()
335 (mode_reg | REG_MODE_BMM) : in ctucan_set_mode()
336 (mode_reg & ~REG_MODE_BMM); in ctucan_set_mode()
339 (mode_reg | REG_MODE_FDE) : in ctucan_set_mode()
340 (mode_reg & ~REG_MODE_FDE); in ctucan_set_mode()
343 (mode_reg | REG_MODE_ACF) : in ctucan_set_mode()
344 (mode_reg & ~REG_MODE_ACF); in ctucan_set_mode()
359 mode_reg &= ~REG_MODE_TSTM; in ctucan_set_mode()
379 u32 mode_reg; in ctucan_chip_start() local
[all …]
/drivers/clk/spear/
A Dclk-vco-pll.c199 mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK; in clk_vco_recalc_rate()
241 val = readl_relaxed(vco->mode_reg); in clk_vco_set_rate()
244 writel_relaxed(val, vco->mode_reg); in clk_vco_set_rate()
274 unsigned long flags, void __iomem *mode_reg, void __iomem in clk_register_vco_pll() argument
285 if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg || in clk_register_vco_pll()
300 vco->mode_reg = mode_reg; in clk_register_vco_pll()
312 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
A Dclk.h92 void __iomem *mode_reg; member
122 unsigned long flags, void __iomem *mode_reg, void __iomem
/drivers/gpu/drm/nouveau/dispnv04/
A Ddfp.c95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_disable()
122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
207 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_dfp_prepare_sel_clk()
251 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_prepare()
288 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()
464 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control = in nv04_dfp_commit()
557 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); in nv04_lvds_dpms()
558 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0; in nv04_lvds_dpms()
560 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv04_lvds_dpms()
A Dtvnv04.c79 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_tv_dpms()
107 struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv04_tv_bind()
146 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_tv_mode_set()
A Dcrtc.c67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_digital_vibrance()
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_image_sharpening()
124 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_calc_state_ext()
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_vga()
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()
665 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv_crtc_mode_set()
675 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_save()
737 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_commit()
786 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; in nv_crtc_gamma_load()
797 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_gamma_load()
[all …]
/drivers/media/i2c/
A Dlm3646.c74 u8 mode_reg; member
87 REG_ENABLE, flash->mode_reg | MODE_SHDN); in lm3646_mode_ctrl()
90 REG_ENABLE, flash->mode_reg | MODE_TORCH); in lm3646_mode_ctrl()
93 REG_ENABLE, flash->mode_reg | MODE_FLASH); in lm3646_mode_ctrl()
303 flash->mode_reg = reg_val & 0xfc; in lm3646_init_device()
/drivers/net/ethernet/
A Ddnet.c175 u32 mode_reg, ctl_reg; in dnet_handle_link_change() local
181 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); in dnet_handle_link_change()
201 mode_reg |= DNET_INTERNAL_MODE_GBITEN; in dnet_handle_link_change()
205 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; in dnet_handle_link_change()
220 mode_reg |= in dnet_handle_link_change()
223 mode_reg &= in dnet_handle_link_change()
236 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); in dnet_handle_link_change()
/drivers/mfd/
A Dmenelaus.c440 u8 mode_reg; member
469 ret = menelaus_write_reg(vtg->mode_reg, mode); in menelaus_set_voltage()
563 .mode_reg = MENELAUS_LDO_CTRL3,
592 .mode_reg = MENELAUS_LDO_CTRL4,
632 .mode_reg = MENELAUS_DCDC_CTRL2,
640 .mode_reg = MENELAUS_DCDC_CTRL3,
677 .mode_reg = MENELAUS_LDO_CTRL7,
707 .mode_reg = MENELAUS_LDO_CTRL6,
/drivers/net/ethernet/stmicro/stmmac/
A Ddwmac-stm32.c103 u32 mode_reg; /* MAC glue-logic mode register */ member
238 u32 reg = dwmac->mode_reg; in stm32mp1_configure_pmcr()
294 u32 reg = dwmac->mode_reg; in stm32mp2_configure_syscfg()
359 u32 reg = dwmac->mode_reg; in stm32mcu_set_mode()
418 1, &dwmac->mode_reg); in stm32_dwmac_parse_data()
/drivers/tty/serial/
A Dxilinx_uartps.c822 unsigned int ctrl_reg, mode_reg; in cdns_uart_set_termios() local
885 mode_reg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_termios()
925 cval |= mode_reg & 1; in cdns_uart_set_termios()
1171 u32 mode_reg; in cdns_uart_set_mctrl() local
1178 mode_reg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_mctrl()
1181 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; in cdns_uart_set_mctrl()
1190 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; in cdns_uart_set_mctrl()
1192 mode_reg |= CDNS_UART_MR_CHMODE_NORM; in cdns_uart_set_mctrl()
1195 writel(mode_reg, port->membase + CDNS_UART_MR); in cdns_uart_set_mctrl()
/drivers/mmc/host/
A Datmel-mci.c366 u32 mode_reg; member
1284 atmci_writel(host, ATMCI_MR, host->mode_reg); in atmci_start_request()
1431 if (!host->mode_reg) { in atmci_set_ios()
1463 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) in atmci_set_ios()
1473 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); in atmci_set_ios()
1482 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); in atmci_set_ios()
1493 atmci_writel(host, ATMCI_MR, host->mode_reg); in atmci_set_ios()
1514 if (host->mode_reg) { in atmci_set_ios()
1517 host->mode_reg = 0; in atmci_set_ios()
1603 atmci_writel(host, ATMCI_MR, host->mode_reg); in atmci_request_end()
[all …]

Completed in 61 milliseconds

123