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Searched refs:mode_val (Results 1 – 18 of 18) sorted by relevance

/drivers/leds/
A Dleds-netxbig.c49 int *mode_val; member
111 int *mode_val; member
145 int mode_val; in netxbig_led_blink_set() local
154 mode_val = led_dat->mode_val[mode]; in netxbig_led_blink_set()
174 int mode_val; in netxbig_led_set() local
191 mode_val = led_dat->mode_val[mode]; in netxbig_led_set()
216 int mode_val; in sata_store() local
240 mode_val = led_dat->mode_val[mode]; in sata_store()
302 led_dat->mode_val = template->mode_val; in create_netxbig_led()
530 mode_val = in netxbig_leds_get_of_pdata()
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A Dleds-lm3530.c86 enum lm3530_mode mode_val; member
150 return mode_map[i].mode_val; in lm3530_get_mode_from_str()
358 if (drvdata->mode == mode_map[i].mode_val) in mode_show()
/drivers/soc/renesas/
A Dr9a09g056-sys.c41 u32 prr_val, mode_val; in rzv2n_sys_print_id() local
45 mode_val = readl(sysc_base + SYS_LSI_MODE); in rzv2n_sys_print_id()
50 feature_flags |= (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_SEC : 0; in rzv2n_sys_print_id()
60 if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) in rzv2n_sys_print_id()
A Dr9a09g047-sys.c37 u32 prr_val, mode_val; in rzg3e_sys_print_id() local
40 mode_val = readl(sysc_base + SYS_LSI_MODE); in rzg3e_sys_print_id()
52 if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) in rzg3e_sys_print_id()
A Dr9a09g057-sys.c37 u32 prr_val, mode_val; in rzv2h_sys_print_id() local
40 mode_val = readl(sysc_base + SYS_LSI_MODE); in rzv2h_sys_print_id()
52 if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) in rzv2h_sys_print_id()
/drivers/spi/
A Dspi-npcm-pspi.c106 u16 mode_val; in npcm_pspi_set_mode() local
110 mode_val = 0; in npcm_pspi_set_mode()
113 mode_val = NPCM_PSPI_CTL1_SCIDL; in npcm_pspi_set_mode()
116 mode_val = NPCM_PSPI_CTL1_SCM; in npcm_pspi_set_mode()
119 mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM; in npcm_pspi_set_mode()
125 iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_set_mode()
A Dspi-microchip-core.c373 u32 mode_val; in mchp_corespi_set_mode() local
378 mode_val = 0; in mchp_corespi_set_mode()
381 mode_val = CONTROL_SPH; in mchp_corespi_set_mode()
384 mode_val = CONTROL_SPO; in mchp_corespi_set_mode()
387 mode_val = CONTROL_SPH | CONTROL_SPO; in mchp_corespi_set_mode()
400 control |= mode_val; in mchp_corespi_set_mode()
/drivers/regulator/
A Drt6160-regulator.c99 unsigned int mode_val; in rt6160_set_mode() local
103 mode_val = RT6160_FPWM_MASK; in rt6160_set_mode()
106 mode_val = 0; in rt6160_set_mode()
113 return regmap_update_bits(regmap, RT6160_REG_CNTL, RT6160_FPWM_MASK, mode_val); in rt6160_set_mode()
A Drt5759-regulator.c60 unsigned int mode_val; in rt5759_set_mode() local
64 mode_val = 0; in rt5759_set_mode()
67 mode_val = RT5759_FPWM_MASK; in rt5759_set_mode()
74 mode_val); in rt5759_set_mode()
A Drtq2208-regulator.c133 unsigned int mode_val; in rtq2208_get_mode() local
136 ret = regmap_read(rdev->regmap, rdesc->mode_reg, &mode_val); in rtq2208_get_mode()
140 return (mode_val & rdesc->mode_mask) ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL; in rtq2208_get_mode()
A Dcpcap-regulator.c98 mode_mask, volt_mask, mode_val, off_val, \ argument
114 .enable_val = (mode_val), \
/drivers/media/usb/gspca/
A Dkinect.c280 uint8_t mode_val; in sd_start_video() local
288 mode_val = 0x03; in sd_start_video()
293 mode_val = 0x01; in sd_start_video()
338 write_register(gspca_dev, 0x05, mode_val); in sd_start_video()
/drivers/pinctrl/bcm/
A Dpinctrl-bcm6328.c34 unsigned mode_val:1; member
238 .mode_val = 1, \
331 bcm6328_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val); in bcm6328_pinctrl_set_mux()
A Dpinctrl-bcm6318.c35 unsigned mode_val:1; member
302 .mode_val = 1, \
417 bcm6318_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val); in bcm6318_pinctrl_set_mux()
A Dpinctrl-bcm6358.c40 const uint16_t mode_val; member
133 .mode_val = BCM6358_MODE_MUX_##bit, \
259 unsigned int val = pg->mode_val; in bcm6358_pinctrl_set_mux()
/drivers/hwmon/
A Dnct7802.c1044 u8 *mode_val) in nct7802_get_channel_config() argument
1067 *mode_val &= ~MODE_LTD_EN; in nct7802_get_channel_config()
1069 *mode_val |= MODE_LTD_EN; in nct7802_get_channel_config()
1077 *mode_val &= ~(MODE_RTD_MASK << MODE_BIT_OFFSET_RTD(reg - 1)); in nct7802_get_channel_config()
1088 *mode_val |= (RTD_MODE_VOLTAGE & MODE_RTD_MASK) in nct7802_get_channel_config()
1121 *mode_val |= (md & MODE_RTD_MASK) << MODE_BIT_OFFSET_RTD(reg - 1); in nct7802_get_channel_config()
1131 u8 mode_mask = MODE_LTD_EN, mode_val = MODE_LTD_EN; in nct7802_configure_channels() local
1137 &mode_val); in nct7802_configure_channels()
1143 return regmap_update_bits(data->regmap, REG_MODE, mode_mask, mode_val); in nct7802_configure_channels()
/drivers/clk/qcom/
A Dclk-alpha-pll.c1062 u32 mode_val, opmode_val; in trion_pll_is_enabled() local
1065 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
1070 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); in trion_pll_is_enabled()
/drivers/media/dvb-frontends/drx39xyj/
A Ddrxj.c9930 u8 mode_val[4] = { 2, 2, 0, 1 }; in ctrl_set_oob() local
10091 mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6]; in ctrl_set_oob()

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