| /drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| A D | dcn31_dccg.c | 60 int modulo, phase; in dccg31_update_dpp_dto() local
63 modulo = 0xff; // use FF at the end in dccg31_update_dpp_dto()
64 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg31_update_dpp_dto()
73 DPPCLK0_DTO_MODULO, modulo); in dccg31_update_dpp_dto()
573 uint32_t modulo, phase; in dccg31_set_dtbclk_dto() local
576 modulo = params->ref_dtbclk_khz * 1000; in dccg31_set_dtbclk_dto()
577 phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), in dccg31_set_dtbclk_dto()
583 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg31_set_dtbclk_dto()
617 uint32_t modulo, phase; in dccg31_set_audio_dtbclk_dto() local
620 modulo = params->ref_dtbclk_khz * 1000; in dccg31_set_audio_dtbclk_dto()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| A D | dcn21_dccg.c | 52 int modulo = ref_dppclk / 10000; in dccg21_update_dpp_dto() local
69 if (phase > modulo) { in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
90 DPPCLK0_DTO_MODULO, modulo); in dccg21_update_dpp_dto()
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| A D | dcn20_dccg.c | 53 int modulo, phase; in dccg2_update_dpp_dto() local
56 modulo = 0xff; // use FF at the end in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
66 DPPCLK0_DTO_MODULO, modulo); in dccg2_update_dpp_dto()
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| /drivers/net/wan/ |
| A D | hdlc_x25.c | 205 if (state(hdlc)->settings.modulo == 128) in x25_open()
308 new_settings.modulo = 8; in x25_ioctl()
319 (new_settings.modulo != 8 && in x25_ioctl()
320 new_settings.modulo != 128) || in x25_ioctl()
322 (new_settings.modulo == 8 && in x25_ioctl()
324 (new_settings.modulo == 128 && in x25_ioctl()
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| A D | dcn35_dccg.c | 1154 int modulo, phase; in dccg35_update_dpp_dto() local
1157 modulo = 0xff; // use FF at the end in dccg35_update_dpp_dto()
1168 DPPCLK0_DTO_MODULO, modulo); in dccg35_update_dpp_dto()
1364 uint32_t modulo, phase; in dccg35_set_dtbclk_dto() local
1382 modulo = params->ref_dtbclk_khz * 1000; in dccg35_set_dtbclk_dto()
1385 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg35_set_dtbclk_dto()
2132 int modulo, phase; in dccg35_update_dpp_dto_cb() local
2135 modulo = 0xff; // use FF at the end in dccg35_update_dpp_dto_cb()
2149 DPPCLK0_DTO_MODULO, modulo); in dccg35_update_dpp_dto_cb()
2281 uint32_t modulo, phase; in dccg35_set_dtbclk_dto_cb() local
[all …]
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| A D | dcn32_dccg.c | 213 uint32_t modulo, phase; in dccg32_set_dtbclk_dto() local
216 modulo = params->ref_dtbclk_khz * 1000; in dccg32_set_dtbclk_dto()
219 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg32_set_dtbclk_dto()
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| A D | dcn314_dccg.c | 214 uint32_t modulo, phase; in dccg314_set_dtbclk_dto() local
217 modulo = params->ref_dtbclk_khz * 1000; in dccg314_set_dtbclk_dto()
220 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg314_set_dtbclk_dto()
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| /drivers/gpu/drm/meson/ |
| A D | meson_venc.c | 856 static unsigned long modulo(unsigned long a, unsigned long b) in modulo() function
1158 de_h_begin = modulo(readl_relaxed(priv->io_base + in meson_venc_hdmi_mode_set()
1162 de_h_end = modulo(de_h_begin + active_pixels_venc, in meson_venc_hdmi_mode_set()
1196 hs_end = modulo(hs_begin + hsync_pixels_venc, in meson_venc_hdmi_mode_set()
1267 vso_begin_odd = modulo(hs_begin in meson_venc_hdmi_mode_set()
1282 vso_begin_evn = modulo(hs_begin in meson_venc_hdmi_mode_set()
1405 de_h_begin = modulo(readl_relaxed(priv->io_base + in meson_venc_hdmi_mode_set()
1409 de_h_end = modulo(de_h_begin + active_pixels_venc, in meson_venc_hdmi_mode_set()
1459 hs_end = modulo(hs_begin + hsync_pixels_venc, in meson_venc_hdmi_mode_set()
1481 vs_eline_evn = modulo(vs_bline_evn + vsync_lines, in meson_venc_hdmi_mode_set()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| A D | M0209.c | 83 info->modulo = nvbios_rd08(bios, data + 0x01); in nvbios_M0209Ep()
121 u32 bits = (i % M0209E.modulo) * M0209E.bits; in nvbios_M0209Sp()
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| /drivers/clk/mmp/ |
| A D | clk-audio.c | 98 unsigned char modulo; member
146 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_recalc_rate()
212 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_set_rate()
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| A D | dcn401_dccg.c | 83 int modulo, phase; in dccg401_update_dpp_dto() local
86 modulo = 0xff; // use FF at the end in dccg401_update_dpp_dto()
87 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg401_update_dpp_dto()
96 DPPCLK0_DTO_MODULO, modulo); in dccg401_update_dpp_dto()
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| /drivers/dma/ |
| A D | k3dma.c | 597 size_t modulo = DMA_CYCLIC_MAX_PERIOD; in k3_dma_prep_dma_cyclic() local
605 if (avail > modulo) in k3_dma_prep_dma_cyclic()
606 num += DIV_ROUND_UP(avail, modulo) - 1; in k3_dma_prep_dma_cyclic()
619 if (period_len < modulo) in k3_dma_prep_dma_cyclic()
620 modulo = period_len; in k3_dma_prep_dma_cyclic()
623 len = min_t(size_t, avail, modulo); in k3_dma_prep_dma_cyclic()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| A D | M0209.h | 10 u8 modulo; member
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| /drivers/media/dvb-frontends/ |
| A D | dibx000_common.h | 129 u8 modulo; member
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| A D | dib7000m.c | 398 reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) | in dib7000m_reset_pll()
443 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7)); in dib7000mc_reset_pll()
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| A D | dib8000.c | 717 (pll->modulo << 8) | in dib8000_reset_pll()
722 (pll->modulo << 8) | in dib8000_reset_pll()
726 (3 << 10) | (pll->modulo << 8) | in dib8000_reset_pll()
739 dib8000_write_word(state, 904, (pll->modulo << 8)); in dib8000_reset_pll()
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| /drivers/media/usb/go7007/ |
| A D | go7007-fw.c | 417 int modulo, int pict_struct, enum mpeg_frame_type frame) in mpeg1_frame_header() argument
718 int modulo, enum mpeg_frame_type frame) in mpeg4_frame_header() argument
725 if (modulo) in mpeg4_frame_header()
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| /drivers/dma/stm32/ |
| A D | stm32-dma.c | 1359 u32 modulo, burst_size; in stm32_dma_desc_residue() local
1415 modulo = residue % burst_size; in stm32_dma_desc_residue()
1416 if (modulo) in stm32_dma_desc_residue()
1417 residue = residue - modulo + burst_size; in stm32_dma_desc_residue()
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| A D | stm32-mdma.c | 1325 u32 cisr, clar, cbndtr, residue, modulo, burst_size; in stm32_mdma_desc_residue() local
1353 modulo = residue % burst_size; in stm32_mdma_desc_residue()
1354 if (modulo) in stm32_mdma_desc_residue()
1355 residue = residue - modulo + burst_size; in stm32_mdma_desc_residue()
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| /drivers/media/usb/dvb-usb/ |
| A D | dib0700_devices.c | 233 .modulo = 2,
399 .modulo = 0,
668 .modulo = 0,
960 .modulo = 2,
1186 .modulo = 2,
1526 .modulo = 2,
1962 .modulo = 2,
2787 .modulo = 2,
3570 .modulo = 0,
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| A D | cxusb.c | 1083 .modulo = 2,
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| /drivers/net/wireless/broadcom/b43/ |
| A D | dma.c | 960 #define modulo(a, b) ({ \ macro
994 (unsigned long long)modulo(permille_failed, 10), in b43_destroy_dmaring()
996 (unsigned long long)modulo(average_tries, 100)); in b43_destroy_dmaring()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 2355 uint64_t modulo[MAX_PIPES]; in dcn10_align_pixel_clocks() local
2393 modulo[i] = dp_ref_clk_100hz*100; in dcn10_align_pixel_clocks()
2400 modulo[i] = (uint64_t)dp_ref_clk_100hz* in dcn10_align_pixel_clocks()
2405 &modulo[i], true) == false) { in dcn10_align_pixel_clocks()
2421 phase[i], modulo[i]); in dcn10_align_pixel_clocks()
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| /drivers/atm/ |
| A D | fore200e.c | 82 #define FORE200E_NEXT_ENTRY(index, modulo) (index = ((index) + 1) % (modulo)) argument
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| /drivers/scsi/ |
| A D | scsi_debug.c | 7117 int count, modulo; in tweak_cmnd_count() local
7119 modulo = abs(sdebug_every_nth); in tweak_cmnd_count()
7120 if (modulo < 2) in tweak_cmnd_count()
7126 atomic_set(&sdebug_cmnd_count, (count / modulo) * modulo); in tweak_cmnd_count()
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