| /drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| A D | dcn20_mpc.c | 44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
164 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_output_csc()
166 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_output_csc()
222 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
224 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
250 reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
258 reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
262 reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc2_ogam_get_reg_field()
266 reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B; in mpc2_ogam_get_reg_field()
590 const struct dcn20_mpc_shift *mpc_shift, in dcn20_mpc_construct() argument
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| A D | dcn20_mpc.h | 266 const struct dcn20_mpc_shift *mpc_shift; member
273 const struct dcn20_mpc_shift *mpc_shift,
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn401/ |
| A D | dcn401_mpc.c | 41 mpc401->mpc_shift->field_name, mpc401->mpc_mask->field_name
316 gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C11_A; in mpc_program_gamut_remap()
318 gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C12_A; in mpc_program_gamut_remap()
350 gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A; in mpc_program_gamut_remap()
352 gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C12_A; in mpc_program_gamut_remap()
482 gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C11_A; in mpc_read_gamut_remap()
484 gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C12_A; in mpc_read_gamut_remap()
505 gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A; in mpc_read_gamut_remap()
507 gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C12_A; in mpc_read_gamut_remap()
621 const struct dcn401_mpc_shift *mpc_shift, in dcn401_mpc_construct() argument
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| A D | dcn401_mpc.h | 195 const struct dcn401_mpc_shift *mpc_shift; member
202 const struct dcn401_mpc_shift *mpc_shift,
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_mpc.c | 40 mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
106 const struct dcn201_mpc_shift *mpc_shift, in dcn201_mpc_construct() argument
117 mpc201->mpc_shift = mpc_shift; in dcn201_mpc_construct()
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| A D | dcn201_mpc.h | 75 const struct dcn201_mpc_shift *mpc_shift; member
82 const struct dcn201_mpc_shift *mpc_shift,
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn30/ |
| A D | dcn30_mpc.c | 41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
209 reg->shifts.field_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
1094 gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A; in program_gamut_remap()
1096 gam_regs.shifts.csc_c12 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C12_A; in program_gamut_remap()
1170 gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A; in read_gamut_remap()
1324 ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A; in mpc3_set_output_csc()
1326 ocsc_regs.shifts.csc_c12 = mpc30->mpc_shift->MPC_OCSC_C12_A; in mpc3_set_output_csc()
1366 ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A; in mpc3_set_ocsc_default()
1368 ocsc_regs.shifts.csc_c12 = mpc30->mpc_shift->MPC_OCSC_C12_A; in mpc3_set_ocsc_default()
1554 const struct dcn30_mpc_shift *mpc_shift, in dcn30_mpc_construct() argument
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| A D | dcn30_mpc.h | 997 const struct dcn30_mpc_shift *mpc_shift; member
1005 const struct dcn30_mpc_shift *mpc_shift,
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn32/ |
| A D | dcn32_mpc.c | 42 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
143 reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET; in mpc32_post1dlut_get_reg_field()
145 …reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENT… in mpc32_post1dlut_get_reg_field()
147 reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET; in mpc32_post1dlut_get_reg_field()
149 …reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENT… in mpc32_post1dlut_get_reg_field()
152 reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B; in mpc32_post1dlut_get_reg_field()
154 reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B; in mpc32_post1dlut_get_reg_field()
156 reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B; in mpc32_post1dlut_get_reg_field()
160 reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B; in mpc32_post1dlut_get_reg_field()
1030 const struct dcn30_mpc_shift *mpc_shift, in dcn32_mpc_construct() argument
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| A D | dcn32_mpc.h | 328 const struct dcn30_mpc_shift *mpc_shift,
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn10/ |
| A D | dcn10_mpc.c | 37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
501 const struct dcn_mpc_shift *mpc_shift, in dcn10_mpc_construct() argument
512 mpc10->mpc_shift = mpc_shift; in dcn10_mpc_construct()
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| A D | dcn10_mpc.h | 130 const struct dcn_mpc_shift *mpc_shift; member
137 const struct dcn_mpc_shift *mpc_shift,
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| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 493 static const struct dcn201_mpc_shift mpc_shift = { variable
734 &mpc_shift, in dcn201_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 640 static const struct dcn30_mpc_shift mpc_shift = { variable
655 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn302_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 605 static const struct dcn30_mpc_shift mpc_shift = { variable
620 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn303_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 382 static const struct dcn_mpc_shift mpc_shift = { variable
678 &mpc_shift, in dcn10_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 290 static const struct dcn20_mpc_shift mpc_shift = { variable
1072 &mpc_shift, in dcn21_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 526 static const struct dcn30_mpc_shift mpc_shift = { variable
806 &mpc_shift, in dcn301_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 595 static const struct dcn30_mpc_shift mpc_shift = { variable
1006 &mpc_shift, in dcn31_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 608 static const struct dcn30_mpc_shift mpc_shift = { variable
1071 &mpc_shift, in dcn31_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 601 static const struct dcn30_mpc_shift mpc_shift = { variable
1014 &mpc_shift, in dcn31_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 461 static const struct dcn30_mpc_shift mpc_shift = { variable
957 &mpc_shift, in dcn321_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 473 static const struct dcn30_mpc_shift mpc_shift = { variable
965 &mpc_shift, in dcn35_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 600 static const struct dcn30_mpc_shift mpc_shift = { variable
1012 &mpc_shift, in dcn31_mpc_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 453 static const struct dcn30_mpc_shift mpc_shift = { variable
945 &mpc_shift, in dcn35_mpc_create()
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