| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 1433 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1631 pool->base.mpcc_count = j; in dcn301_resource_construct()
1648 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 299 unsigned int mpcc_count; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 1105 pool->base.mpcc_count = 5; in dcn201_resource_construct()
1265 pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count); in dcn201_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| A D | dcn30_hwseq.c | 179 for (i = 0; i < pool->mpcc_count; i++) { in dcn30_log_color_state()
437 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 1218 pool->mpcc_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1425 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 1160 pool->mpcc_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1358 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 395 for (i = 0; i < pool->mpcc_count; i++) { in dcn10_get_mpcc_states()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 1748 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
1952 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn316_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 1831 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn314_resource_construct()
2059 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn314_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 1902 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2136 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn31_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 1837 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn35_resource_construct()
2094 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn35_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 1872 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
2084 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn315_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 1809 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn351_resource_construct()
2065 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn351_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 1810 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn36_resource_construct()
2067 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn36_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 2300 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn30_resource_construct()
2528 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 2413 pool->base.mpcc_count = 5; in dcn20_resource_construct()
2417 pool->base.mpcc_count = 6; in dcn20_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 1631 pool->base.mpcc_count = j; in dcn10_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 527 for (i = 0; i < pool->mpcc_count; i++) { in dcn10_log_color_state()
545 for (i = 0; i < pool->mpcc_count; i++) { in dcn10_log_color_state()
561 for (i = 0; i < pool->mpcc_count; i++) { in dcn10_log_color_state()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 1640 pool->base.mpcc_count = j; in dcn21_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 1701 pool->base.mpcc_count = num_pipes; in dcn321_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 1873 pool->base.mpcc_count = num_pipes; in dcn401_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 2193 pool->base.mpcc_count = num_pipes; in dcn32_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 168 for (i = 0; i < pool->mpcc_count; i++) { in dcn20_log_color_state()
|