| /drivers/gpu/drm/amd/display/dc/mpc/dcn10/ |
| A D | dcn10_mpc.c | 336 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc1_init_mpcc() argument
338 mpcc->mpcc_id = mpcc_inst; in mpc1_init_mpcc()
444 int mpcc_inst, in mpc1_read_mpcc_state() argument
449 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc1_read_mpcc_state()
450 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc1_read_mpcc_state()
451 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc1_read_mpcc_state()
452 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, in mpc1_read_mpcc_state()
456 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, in mpc1_read_mpcc_state()
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| A D | dcn10_mpc.h | 194 int mpcc_inst,
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| A D | dcn20_mpc.c | 509 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc2_init_mpcc() argument
511 mpcc->mpcc_id = mpcc_inst; in mpc2_init_mpcc()
545 int mpcc_inst, in mpc2_read_mpcc_state() argument
550 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc2_read_mpcc_state()
551 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc2_read_mpcc_state()
552 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc2_read_mpcc_state()
553 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, in mpc2_read_mpcc_state()
557 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, in mpc2_read_mpcc_state()
561 REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_inst], in mpc2_read_mpcc_state()
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_mpc.c | 62 static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc201_init_mpcc() argument
64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| A D | dcn30_hwseq.c | 436 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
437 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
443 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
458 wb_info->mpcc_inst); in dcn30_update_writeback()
536 wb_info->mpcc_inst); in dcn30_enable_writeback()
600 wb_info.mpcc_inst = -1; in dcn30_program_all_writeback_pipes_in_tree()
608 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
613 if (wb_info.mpcc_inst == -1) { in dcn30_program_all_writeback_pipes_in_tree()
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn30/ |
| A D | dcn30_mpc.c | 1049 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc3_init_mpcc() argument
1051 mpcc->mpcc_id = mpcc_inst; in mpc3_init_mpcc()
1473 int mpcc_inst, in mpc3_read_mpcc_state() argument
1479 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc3_read_mpcc_state()
1480 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc3_read_mpcc_state()
1481 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc3_read_mpcc_state()
1482 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, in mpc3_read_mpcc_state()
1486 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, in mpc3_read_mpcc_state()
1492 if (rmu_status == mpcc_inst) { in mpc3_read_mpcc_state()
1512 REG_GET_2(MPCC_OGAM_CONTROL[mpcc_inst], in mpc3_read_mpcc_state()
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| A D | dcn30_mpc.h | 1099 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | pg_cntl.h | 45 void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on);
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| A D | mpc.h | 364 int mpcc_inst,
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| /drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| A D | dcn35_pg_cntl.c | 357 unsigned int mpcc_inst, bool power_on) in pg_cntl35_mpcc_pg_control() argument
362 if (mpcc_inst < MAX_PIPES) in pg_cntl35_mpcc_pg_control()
363 pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on; in pg_cntl35_mpcc_pg_control()
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| A D | dcn35_pg_cntl.h | 179 unsigned int mpcc_inst, bool power_on);
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_hw_sequencer.c | 1221 int mpcc_inst; in hwss_wait_for_outstanding_hw_updates() local
1242 mpcc_inst = hubp->inst; in hwss_wait_for_outstanding_hw_updates()
1246 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) { in hwss_wait_for_outstanding_hw_updates()
1247 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); in hwss_wait_for_outstanding_hw_updates()
1248 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; in hwss_wait_for_outstanding_hw_updates()
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| A D | dc_resource.c | 2541 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_split_pipe()
3694 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst; in acquire_resource_from_hw_enabled_state()
3699 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); in acquire_resource_from_hw_enabled_state()
3702 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = in acquire_resource_from_hw_enabled_state()
3706 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = in acquire_resource_from_hw_enabled_state()
3838 pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in acquire_otg_master_pipe_for_stream()
5460 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 315 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
323 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_init_hw()
411 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_plane_atomic_disconnect()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dmub_psr.c | 341 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 1428 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect()
1639 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn10_init_pipes()
1646 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_init_pipes()
3508 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) in get_hubp_by_inst() argument
3513 if (res_pool->hubps[i]->inst == mpcc_inst) in get_hubp_by_inst()
3526 int mpcc_inst; in dcn10_wait_for_mpcc_disconnect() local
3535 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { in dcn10_wait_for_mpcc_disconnect()
3536 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { in dcn10_wait_for_mpcc_disconnect()
3537 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
3541 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
[all …]
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_stream.h | 106 int mpcc_inst; member
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| A D | dc.h | 1877 int mpcc_inst);
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| A D | dcn35_hwseq.c | 807 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn35_init_pipes()
814 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn35_init_pipes()
1043 update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false; in dcn35_calc_blocks_to_gate()
1135 update_state->pg_pipe_res_update[j][new_pipe->plane_res.mpcc_inst] = true; in dcn35_calc_blocks_to_ungate()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 382 uint8_t mpcc_inst; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 1495 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1551 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in dcn20_split_stream_for_mpc()
2167 sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst; in dcn20_acquire_free_pipe_for_layer()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 2762 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2821 free_pipe->plane_res.mpcc_inst = in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2854 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst; in dcn32_acquire_free_pipe_as_secondary_opp_head()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 1024 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn201_acquire_free_pipe_for_layer()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 1105 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_free_pipe_for_layer()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 3190 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn20_fpga_init_hw()
3200 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn20_fpga_init_hw()
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