Home
last modified time | relevance | path

Searched refs:mpll (Results 1 – 25 of 31) sorted by relevance

12

/drivers/clk/mstar/
A Dclk-msc313-mpll.c74 struct msc313_mpll *mpll; in msc313_mpll_probe() local
82 mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL); in msc313_mpll_probe()
83 if (!mpll) in msc313_mpll_probe()
95 if (IS_ERR(mpll->input_div)) in msc313_mpll_probe()
96 return PTR_ERR(mpll->input_div); in msc313_mpll_probe()
98 if (IS_ERR(mpll->output_div)) in msc313_mpll_probe()
107 mpll->clk_data = devm_kzalloc(dev, struct_size(mpll->clk_data, hws, in msc313_mpll_probe()
109 if (!mpll->clk_data) in msc313_mpll_probe()
116 mpll->clk_hw.init = &clk_init; in msc313_mpll_probe()
123 mpll->clk_data->hws[0] = &mpll->clk_hw; in msc313_mpll_probe()
[all …]
A DMakefile7 obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o
/drivers/clk/meson/
A Dclk-mpll.c83 sdm = meson_parm_read(clk->map, &mpll->sdm); in mpll_recalc_rate()
84 n2 = meson_parm_read(clk->map, &mpll->n2); in mpll_recalc_rate()
98 mpll->flags); in mpll_determine_rate()
119 meson_parm_write(clk->map, &mpll->sdm, sdm); in mpll_set_rate()
122 meson_parm_write(clk->map, &mpll->n2, n2); in mpll_set_rate()
137 if (mpll->init_count) in mpll_init()
139 mpll->init_count); in mpll_init()
142 meson_parm_write(clk->map, &mpll->sdm_en, 1); in mpll_init()
145 if (MESON_PARM_APPLICABLE(&mpll->ssen)) { in mpll_init()
152 if (MESON_PARM_APPLICABLE(&mpll->misc)) in mpll_init()
[all …]
A DMakefile9 obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
/drivers/gpu/drm/radeon/
A Dradeon_clocks.c72 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock() local
78 fb_div *= mpll->reference_freq; in radeon_legacy_get_memory_clock()
112 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_read_clocks_OF() local
187 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_get_clock_info() local
219 if (mpll->reference_div < 2) in radeon_get_clock_info()
332 mpll->min_post_div = 1; in radeon_get_clock_info()
333 mpll->max_post_div = 1; in radeon_get_clock_info()
334 mpll->min_ref_div = 2; in radeon_get_clock_info()
335 mpll->max_ref_div = 0xff; in radeon_get_clock_info()
336 mpll->min_feedback_div = 4; in radeon_get_clock_info()
[all …]
A Dradeon_combios.c721 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_combios_get_clock_info() local
762 mpll->reference_freq = RBIOS16(pll_info + 0x26); in radeon_combios_get_clock_info()
763 mpll->reference_div = RBIOS16(pll_info + 0x28); in radeon_combios_get_clock_info()
764 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); in radeon_combios_get_clock_info()
765 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); in radeon_combios_get_clock_info()
768 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); in radeon_combios_get_clock_info()
769 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); in radeon_combios_get_clock_info()
772 mpll->pll_in_min = 40; in radeon_combios_get_clock_info()
773 mpll->pll_in_max = 500; in radeon_combios_get_clock_info()
A Dradeon_atombios.c1136 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_atom_get_clock_info() local
1215 mpll->reference_freq = in radeon_atom_get_clock_info()
1218 mpll->reference_freq = in radeon_atom_get_clock_info()
1220 mpll->reference_div = 0; in radeon_atom_get_clock_info()
1222 mpll->pll_out_min = in radeon_atom_get_clock_info()
1224 mpll->pll_out_max = in radeon_atom_get_clock_info()
1228 if (mpll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1230 mpll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1232 mpll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1235 mpll->pll_in_min = in radeon_atom_get_clock_info()
[all …]
A Drv740_dpm.c250 u32 reference_clock = rdev->clock.mpll.reference_freq; in rv740_populate_mclk_value()
A Drv730_dpm.c169 u32 reference_clock = rdev->clock.mpll.reference_freq; in rv730_populate_mclk_value()
A Dcypress_dpm.c442 u32 ref_clk = rdev->clock.mpll.reference_freq; in cypress_map_clkf_to_ibias()
558 u32 reference_clock = rdev->clock.mpll.reference_freq; in cypress_populate_mclk_value()
A Drv6xx_dpm.c655 u32 ref_clk = rdev->clock.mpll.reference_freq; in rv6xx_program_mclk_spread_spectrum_parameters()
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
A Dnv04.c288 bool mpll = Preg == 0x4020; in setPLL_double_lowregs() local
291 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | in setPLL_double_lowregs()
306 if (mpll) { in setPLL_double_lowregs()
322 Pval |= mpll ? 1 << 12 : 1 << 8; in setPLL_double_lowregs()
326 if (mpll) { in setPLL_double_lowregs()
340 if (mpll) { in setPLL_double_lowregs()
349 if (mpll) { in setPLL_double_lowregs()
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_atomfirmware.c718 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atomfirmware_get_clock_info() local
777 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
779 mpll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
780 mpll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
781 mpll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
782 mpll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
783 mpll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
784 mpll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
785 mpll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
786 mpll->best_vco = 0; in amdgpu_atomfirmware_get_clock_info()
A Damdgpu_atombios.c591 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atombios_get_clock_info() local
663 mpll->reference_freq = in amdgpu_atombios_get_clock_info()
665 mpll->reference_div = 0; in amdgpu_atombios_get_clock_info()
667 mpll->pll_out_min = in amdgpu_atombios_get_clock_info()
669 mpll->pll_out_max = in amdgpu_atombios_get_clock_info()
676 mpll->pll_in_min = in amdgpu_atombios_get_clock_info()
678 mpll->pll_in_max = in amdgpu_atombios_get_clock_info()
686 mpll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
687 mpll->max_post_div = 1; in amdgpu_atombios_get_clock_info()
688 mpll->min_ref_div = 2; in amdgpu_atombios_get_clock_info()
[all …]
A Damdgpu.h432 struct amdgpu_pll mpll; member
/drivers/phy/qualcomm/
A Dphy-qcom-ipq806x-usb.c125 u32 mpll; member
406 data |= SSPHY_MPLL(phy_dwc3->mpll); in qcom_ipq806x_usb_ss_phy_init()
532 if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll)) in qcom_ipq806x_usb_phy_probe()
533 phy_dwc3->mpll = SSPHY_MPLL_VALUE; in qcom_ipq806x_usb_phy_probe()
/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dramnv50.c225 struct nvbios_pll mpll; in nv50_ram_calc() local
327 ret = nvbios_pll_parse(bios, 0x004008, &mpll); in nv50_ram_calc()
328 mpll.vco2.max_freq = 0; in nv50_ram_calc()
330 ret = nv04_pll_calc(subdev, &mpll, freq, in nv50_ram_calc()
348 r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16); in nv50_ram_calc()
/drivers/clk/imx/
A Dclk-imx35.c64 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
A Dclk-imx31.c39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
A Dclk-imx25.c54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
/drivers/clk/samsung/
A Dclk-exynos5410.c62 apll, cpll, epll, mpll, enumerator
247 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
A Dclk-s5pv210.c68 mpll, enumerator
717 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
729 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
A Dclk-exynos5250.c109 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator
739 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
A Dclk-exynos4.c150 apll, mpll, epll, vpll, enumerator
1154 [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1165 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
A Dclk-exynos5420.c154 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1482 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,

Completed in 72 milliseconds

12