Searched refs:mpllb (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | intel_cx0_phy.c | 988 .mpllb = { 0x50e1,
1013 .mpllb = { 0x50fd,
1038 .mpllb = { 0x30a8,
1063 .mpllb = { 0x30e1,
1088 .mpllb = { 0x10af,
2297 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2298 pll_state->mpllb[5] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2509 hw_state->mpllb[i]); in intel_c20pll_dump_hw_state()
3489 if (memcmp(&a->mpllb, &b->mpllb, sizeof(a->mpllb)) != 0) in mtl_compare_hw_state_c20()
3549 INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], in intel_c20pll_state_verify()
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| A D | intel_dpll_mgr.h | 256 u16 mpllb[11]; member
277 struct intel_mpllb_state mpllb; member
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| A D | intel_snps_phy.c | 1803 crtc_state->dpll_hw_state.mpllb = *tables[i]; in intel_mpllb_calc_state()
1810 intel_snps_hdmi_pll_compute_mpllb(&crtc_state->dpll_hw_state.mpllb, in intel_mpllb_calc_state()
1823 const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; in intel_mpllb_enable()
1988 const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb; in intel_mpllb_state_verify()
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| A D | intel_ddi.c | 4256 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4257 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
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