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Searched refs:msix_ctrl (Results 1 – 3 of 3) sorted by relevance

/drivers/pci/msi/
A Dmsi.h45 desc->pci.msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT; in pci_msix_mask()
46 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl); in pci_msix_mask()
53 desc->pci.msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; in pci_msix_unmask()
54 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl); in pci_msix_unmask()
A Dmsi.c212 u32 ctrl = desc->pci.msix_ctrl; in pci_write_msg_msix()
618 desc->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); in msix_prepare_msi_desc()
878 pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl); in __pci_restore_msix_state()
959 msi_desc->pci.msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_ST; in pci_msix_write_tph_tag()
960 msi_desc->pci.msix_ctrl |= FIELD_PREP(PCI_MSIX_ENTRY_CTRL_ST, tag); in pci_msix_write_tph_tag()
961 pci_msix_write_vector_ctrl(msi_desc, msi_desc->pci.msix_ctrl); in pci_msix_write_tph_tag()
/drivers/net/ethernet/huawei/hinic/
A Dhinic_hw_if.c43 u32 msix_ctrl, addr; in hinic_msix_attr_set() local
48 msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | in hinic_msix_attr_set()
56 hinic_hwif_write_reg(hwif, addr, msix_ctrl); in hinic_msix_attr_set()
69 u32 msix_ctrl, addr; in hinic_msix_attr_cnt_clear() local
74 msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER); in hinic_msix_attr_cnt_clear()
77 hinic_hwif_write_reg(hwif, addr, msix_ctrl); in hinic_msix_attr_cnt_clear()

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