| /drivers/phy/mediatek/ |
| A D | phy-mtk-mipi-csi-0-5.c | 58 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
59 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
60 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
61 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_BW, 1); in mtk_phy_csi_dphy_ana_eq_tune()
85 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, in mtk_mipi_phy_power_on()
107 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, in mtk_mipi_phy_power_on()
110 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, in mtk_mipi_phy_power_on()
113 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, in mtk_mipi_phy_power_on()
122 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA, in mtk_mipi_phy_power_on()
124 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA, in mtk_mipi_phy_power_on()
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| A D | phy-mtk-hdmi-mt8195.c | 39 mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, 3); in mtk_phy_tmds_clk_ratio()
63 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IC, 0x1); in mtk_hdmi_pll_perf()
64 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BR, 0x2); in mtk_hdmi_pll_perf()
65 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IR, 0x2); in mtk_hdmi_pll_perf()
70 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_HREN, 0x1); in mtk_hdmi_pll_perf()
71 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_LVR_SEL, 0x1); in mtk_hdmi_pll_perf()
98 mtk_phy_update_field(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_BG_VREF_SEL, 0x2); in mtk_hdmi_pll_set_hw()
100 mtk_phy_update_field(regs + HDMI_1_CFG_9, RG_HDMITX21_SLDO_VREF_SEL, 0x2); in mtk_hdmi_pll_set_hw()
103 mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_INTR_CAL, 0x11); in mtk_hdmi_pll_set_hw()
182 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0, 0x2); in mtk_hdmi_pll_set_hw()
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| A D | phy-mtk-hdmi-mt2701.c | 116 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1); in mtk_hdmi_pll_set_rate()
117 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1); in mtk_hdmi_pll_set_rate()
119 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1); in mtk_hdmi_pll_set_rate()
120 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19); in mtk_hdmi_pll_set_rate()
121 mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2); in mtk_hdmi_pll_set_rate()
122 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc); in mtk_hdmi_pll_set_rate()
123 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2); in mtk_hdmi_pll_set_rate()
124 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1); in mtk_hdmi_pll_set_rate()
129 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28); in mtk_hdmi_pll_set_rate()
130 mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28); in mtk_hdmi_pll_set_rate()
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| A D | phy-mtk-tphy.c | 474 mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1, in u2_phy_params_write()
581 mtk_phy_update_field(phyd + U3P_U3_PHYD_RSV, in u3_phy_params_write()
586 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, in u3_phy_params_write()
859 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2); in u2_phy_instance_init()
990 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1, in pcie_phy_instance_init()
993 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2, in pcie_phy_instance_init()
1169 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, in u2_phy_props_set()
1173 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, in u2_phy_props_set()
1181 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, in u2_phy_props_set()
1186 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, in u2_phy_props_set()
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| A D | phy-mtk-xsphy.c | 141 mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT, in u2_phy_slew_rate_calibrate()
173 mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val); in u2_phy_slew_rate_calibrate()
290 mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL, in u2_phy_props_set()
294 mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, in u2_phy_props_set()
298 mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL, in u2_phy_props_set()
302 mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL, in u2_phy_props_set()
312 mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00, in u3_phy_props_set()
316 mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04, in u3_phy_props_set()
320 mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14, in u3_phy_props_set()
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| A D | phy-mtk-pcie.c | 92 mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL, in mtk_pcie_efuse_set_lane()
95 mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL, in mtk_pcie_efuse_set_lane()
98 mtk_phy_update_field(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL, in mtk_pcie_efuse_set_lane()
119 mtk_phy_update_field(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG, in mtk_pcie_phy_init()
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| A D | phy-mtk-hdmi-mt8173.c | 160 mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div); in mtk_hdmi_pll_set_rate()
166 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV, div); in mtk_hdmi_pll_set_rate()
171 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_DIVEN, 0x2); in mtk_hdmi_pll_set_rate()
196 mtk_phy_update_field(base + HDMI_CON3, RG_HDMITX_DRV_IMP_EN, imp_en); in mtk_hdmi_pll_set_rate()
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| A D | phy-mtk-mipi-dsi-mt8183.c | 83 mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0); in mtk_mipi_tx_pll_enable()
149 mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL, in mtk_mipi_tx_power_on_signal()
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| A D | phy-mtk-io.h | 40 #define mtk_phy_update_field(reg, mask, val) \ macro
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| A D | phy-mtk-mipi-dsi-mt8173.c | 207 mtk_phy_update_field(base + MIPITX_DSI_PLL_TOP, in mtk_mipi_tx_pll_prepare()
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