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Searched refs:mtr (Results 1 – 17 of 17) sorted by relevance

/drivers/infiniband/hw/hns/
A Dhns_roce_mr.c571 if (mtr->umem) { in mtr_free_bufs()
573 mtr->umem = NULL; in mtr_free_bufs()
577 if (mtr->kmem) { in mtr_free_bufs()
579 mtr->kmem = NULL; in mtr_free_bufs()
593 mtr->kmem = NULL; in mtr_alloc_bufs()
602 mtr->umem = NULL; in mtr_alloc_bufs()
638 return mtr->hem_cfg.is_direct && mtr->hem_cfg.region_count > 1; in need_split_huge_page()
657 if (mtr->umem) in mtr_map_bufs()
862 if (mtr->umem) in get_best_hop_num()
933 pgoff = mtr->umem ? mtr->umem->address & ~PAGE_MASK : 0; in mtr_init_buf_cfg()
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A Dhns_roce_device.h417 struct hns_roce_mtr mtr; member
438 struct hns_roce_mtr mtr; member
607 struct hns_roce_mtr mtr; member
705 struct hns_roce_mtr mtr; member
1180 static inline dma_addr_t hns_roce_get_mtr_ba(struct hns_roce_mtr *mtr) in hns_roce_get_mtr_ba() argument
1182 return mtr->hem_cfg.root_ba; in hns_roce_get_mtr_ba()
1185 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1187 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1192 struct hns_roce_mtr *mtr);
1193 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
A Dhns_roce_cq.c138 ret = hns_roce_mtr_find(hr_dev, &hr_cq->mtr, 0, mtts, ARRAY_SIZE(mtts)); in alloc_cqc()
159 hns_roce_get_mtr_ba(&hr_cq->mtr)); in alloc_cqc()
210 ret = hns_roce_mtr_create(hr_dev, &hr_cq->mtr, &buf_attr, in alloc_cq_buf()
221 hns_roce_mtr_destroy(hr_dev, &hr_cq->mtr); in free_cq_buf()
A Dhns_roce_srq.c182 ret = hns_roce_mtr_create(hr_dev, &idx_que->mtr, &buf_attr, in alloc_srq_idx()
205 hns_roce_mtr_destroy(hr_dev, &idx_que->mtr); in alloc_srq_idx()
216 hns_roce_mtr_destroy(hr_dev, &idx_que->mtr); in free_srq_idx()
A Dhns_roce_hw_v2.c879 return hns_roce_buf_offset(idx_que->mtr.kmem, in get_idx_buf()
4408 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); in config_qp_rq_buf()
4484 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, in config_qp_sq_buf()
5797 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr); in hns_roce_v2_write_srqc_index_queue()
6221 aeqe = hns_roce_buf_offset(eq->mtr.kmem, in next_aeqe_sw_v2()
6290 ceqe = hns_roce_buf_offset(eq->mtr.kmem, in next_ceqe_sw_v2()
6530 hns_roce_mtr_destroy(hr_dev, &eq->mtr); in free_eq_buf()
6577 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, in config_eqc()
6584 bt_ba = hns_roce_get_mtr_ba(&eq->mtr); in config_eqc()
6594 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); in config_eqc()
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A Dhns_roce_qp.c783 ret = hns_roce_mtr_create(hr_dev, &hr_qp->mtr, &buf_attr, in alloc_qp_buf()
803 hns_roce_mtr_destroy(hr_dev, &hr_qp->mtr); in free_qp_buf()
1535 return hns_roce_buf_offset(hr_qp->mtr.kmem, offset); in get_wqe()
/drivers/edac/
A Di5400_edac.c287 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) argument
288 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) argument
289 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) argument
290 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) argument
292 #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) argument
294 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument
296 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument
865 int mtr; in determine_mtr() local
884 return mtr; in determine_mtr()
923 int mtr; in handle_channel() local
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A Di7300_edac.c173 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) argument
174 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) argument
175 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) argument
176 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) argument
177 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) argument
178 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument
180 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument
181 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument
595 mtr = pvt->mtr[slot][branch]; in decode_mtr()
674 return mtr; in decode_mtr()
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A Di5000_edac.c279 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8)) argument
280 #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4) argument
281 #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4) argument
283 #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1) argument
285 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) argument
286 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) argument
287 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) argument
953 int mtr; in determine_mtr() local
960 return mtr; in determine_mtr()
995 int mtr; in handle_channel() local
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A Dsb_edac.c215 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) argument
216 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) argument
217 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) argument
218 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) argument
219 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) argument
709 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); in numrank()
722 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); in numrow()
735 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); in numcol()
952 switch (mtr) { in __ibridge_get_width()
1614 u32 mtr, amap = 0; in __populate_dimms() local
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A Di5100_edac.c329 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; member
654 if (!priv->mtr[chan][chan_rank].present) in i5100_npages()
659 priv->mtr[chan][chan_rank].numcol + in i5100_npages()
660 priv->mtr[chan][chan_rank].numrow + in i5100_npages()
661 priv->mtr[chan][chan_rank].numbank; in i5100_npages()
685 priv->mtr[i][j].present = i5100_mtr_present(w); in i5100_init_mtr()
686 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); in i5100_init_mtr()
687 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); in i5100_init_mtr()
689 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); in i5100_init_mtr()
690 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w); in i5100_init_mtr()
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A Dskx_common.c303 static int get_width(u32 mtr) in get_width() argument
305 switch (GET_BITFIELD(mtr, 8, 9)) { in get_width()
427 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, in skx_get_dimm_info() argument
435 ranks = numrank(mtr); in skx_get_dimm_info()
436 rows = numrow(mtr); in skx_get_dimm_info()
437 cols = imc->hbm_mc ? 6 : numcol(mtr); in skx_get_dimm_info()
468 dimm->dtype = get_width(mtr); in skx_get_dimm_info()
A Dskx_base.c180 u32 mtr, mcmtr, amap, mcddrtcfg; in skx_get_dimm_config() local
196 0x80 + 4 * j, &mtr); in skx_get_dimm_config()
197 if (IS_DIMM_PRESENT(mtr)) { in skx_get_dimm_config()
198 ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j, cfg); in skx_get_dimm_config()
A Di10nm_base.c1065 u32 mtr, mcddrtcfg = 0; in i10nm_get_dimm_config() local
1080 mtr = I10NM_GET_DIMMMTR(imc, i, j); in i10nm_get_dimm_config()
1082 mtr, mcddrtcfg, imc->mc, i, j); in i10nm_get_dimm_config()
1084 if (IS_DIMM_PRESENT(mtr)) in i10nm_get_dimm_config()
1085 ndimms += skx_get_dimm_info(mtr, 0, 0, dimm, in i10nm_get_dimm_config()
A Dskx_common.h302 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
/drivers/net/ethernet/mellanox/mlx5/core/
A Dhwmon.c60 MLX5_SET(mtmp_reg, mtmp_in, mtr, 1); in mlx5_hwmon_reset_max_temp()
/drivers/net/ethernet/mellanox/mlxsw/
A Dreg.h9517 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);

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