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Searched refs:mul (Results 1 – 25 of 72) sorted by relevance

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/drivers/clk/
A Dclk-vt8500.c455 u32 mul; in wm8750_find_pll_bits() local
464 for (mul = 0; mul <= 255; mul++) { in wm8750_find_pll_bits()
472 *multiplier = mul; in wm8750_find_pll_bits()
480 *multiplier = mul; in wm8750_find_pll_bits()
503 u32 mul; in wm8850_find_pll_bits() local
512 for (mul = 0; mul <= 127; mul++) { in wm8850_find_pll_bits()
513 tclk = parent_rate * ((mul + 1) * 2) / in wm8850_find_pll_bits()
520 *multiplier = mul; in wm8850_find_pll_bits()
528 *multiplier = mul; in wm8850_find_pll_bits()
550 u32 filter, mul, div1, div2; in vtwm_pll_set_rate() local
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A Dclk-cdce706.c73 unsigned mul; member
173 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
190 unsigned long mul, div; in cdce706_pll_round_rate() local
199 &mul, &div); in cdce706_pll_round_rate()
200 hwd->mul = mul; in cdce706_pll_round_rate()
205 __func__, hwd->idx, mul, div); in cdce706_pll_round_rate()
216 unsigned long mul = hwd->mul, div = hwd->div; in cdce706_pll_set_rate() local
221 __func__, hwd->idx, mul, div); in cdce706_pll_set_rate()
297 unsigned long mul, div; in cdce706_divider_determine_rate() local
305 &mul, &div); in cdce706_divider_determine_rate()
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A Dclk-nomadik.c231 u8 mul; in pll_clk_recalc_rate() local
234 mul = (val >> 8) & 0x3FU; in pll_clk_recalc_rate()
235 mul += 2; in pll_clk_recalc_rate()
237 return (parent_rate * mul) >> div; in pll_clk_recalc_rate()
241 u8 mul; in pll_clk_recalc_rate() local
243 mul = (val >> 24) & 0x3FU; in pll_clk_recalc_rate()
244 mul += 2; in pll_clk_recalc_rate()
245 return (parent_rate * mul); in pll_clk_recalc_rate()
A Dclk-moxart.c21 unsigned int mul; in moxart_of_pll_clk_init() local
34 mul = readl(base + 0x30) >> 3 & 0x3f; in moxart_of_pll_clk_init()
43 hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1); in moxart_of_pll_clk_init()
/drivers/clk/actions/
A Dowl-factor.c34 *mul = clkt->mul; in _get_table_div_mul()
51 calc_rate = parent_rate * clkt->mul; in _get_table_val()
85 try_parent_rate = rate * clkt->div / clkt->mul; in owl_clk_val_best()
89 __func__, clkt->val, clkt->mul, clkt->div, in owl_clk_val_best()
125 unsigned int val, mul = 0, div = 1; in owl_factor_helper_round_rate() local
128 _get_table_div_mul(clkt, val, &mul, &div); in owl_factor_helper_round_rate()
130 return *parent_rate * mul / div; in owl_factor_helper_round_rate()
149 u32 reg, val, mul, div; in owl_factor_helper_recalc_rate() local
152 mul = 0; in owl_factor_helper_recalc_rate()
159 _get_table_div_mul(clkt, val, &mul, &div); in owl_factor_helper_recalc_rate()
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A Dowl-pll.c20 u32 mul; in owl_pll_calculate_mul() local
22 mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq); in owl_pll_calculate_mul()
23 if (mul < pll_hw->min_mul) in owl_pll_calculate_mul()
24 mul = pll_hw->min_mul; in owl_pll_calculate_mul()
25 else if (mul > pll_hw->max_mul) in owl_pll_calculate_mul()
26 mul = pll_hw->max_mul; in owl_pll_calculate_mul()
28 return mul & mul_mask(pll_hw); in owl_pll_calculate_mul()
65 u32 mul; in owl_pll_round_rate() local
76 mul = owl_pll_calculate_mul(pll_hw, rate); in owl_pll_round_rate()
78 return pll_hw->bfreq * mul; in owl_pll_round_rate()
/drivers/clk/at91/
A Dclk-pll.c40 u16 mul; member
69 u16 mul; in clk_pll_prepare() local
73 mul = PLL_MUL(pllr, layout); in clk_pll_prepare()
77 (div == pll->div && mul == pll->mul)) in clk_pll_prepare()
118 if (!pll->div || !pll->mul) in clk_pll_recalc_rate()
126 u32 *div, u32 *mul, in clk_pll_get_best_div_mul() argument
226 if (mul) in clk_pll_get_best_div_mul()
227 *mul = bestmul - 1; in clk_pll_get_best_div_mul()
249 u32 mul; in clk_pll_set_rate() local
253 &div, &mul, &index); in clk_pll_set_rate()
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A Dclk-sam9x60-pll.c41 u16 mul; member
78 freq = parent_rate * (frac->mul + 1) + in sam9x60_frac_pll_recalc_rate()
103 (cmul == frac->mul && cfrac == frac->frac)) in sam9x60_frac_pll_set()
114 (frac->mul << core->layout->mul_shift) | in sam9x60_frac_pll_set()
226 frac->mul = nmul - 1; in sam9x60_frac_pll_compute_mul_frac()
271 if (cmul == frac->mul && cfrac == frac->frac) in sam9x60_frac_pll_set_rate_chg()
275 (frac->mul << core->layout->mul_shift) | in sam9x60_frac_pll_set_rate_chg()
677 frac->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val); in sam9x60_clk_register_frac_pll()
/drivers/clk/tegra/
A Dclk-utils.c16 int mul; in div_frac_get() local
21 mul = 1 << frac_width; in div_frac_get()
24 divider_ux1 *= mul; in div_frac_get()
32 divider_ux1 *= mul; in div_frac_get()
34 if (divider_ux1 < mul) in div_frac_get()
37 divider_ux1 -= mul; in div_frac_get()
A Dclk-divider.c40 int div, mul; in clk_frac_div_recalc_rate() local
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
52 div += mul; in clk_frac_div_recalc_rate()
54 rate *= mul; in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_round_rate() local
75 mul = get_mul(divider); in clk_frac_div_round_rate()
77 return DIV_ROUND_UP(output_rate * mul, div + mul); in clk_frac_div_round_rate()
A Dclk-periph-fixed.c57 rate = (unsigned long long)parent_rate * fixed->mul; in tegra_clk_periph_fixed_recalc_rate()
74 unsigned int mul, in tegra_clk_register_periph_fixed() argument
99 fixed->mul = mul; in tegra_clk_register_periph_fixed()
/drivers/cpufreq/
A Dcpufreq-nforce2.c25 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div) argument
69 unsigned char mul, div; in nforce2_calc_fsb() local
71 mul = (pll >> 8) & 0xff; in nforce2_calc_fsb()
75 return NFORCE2_XTAL * mul / div; in nforce2_calc_fsb()
89 unsigned char mul = 0, div = 0; in nforce2_calc_pll() local
93 while (((mul == 0) || (div == 0)) && (tried <= 3)) { in nforce2_calc_pll()
98 mul = xmul; in nforce2_calc_pll()
104 if ((mul == 0) || (div == 0)) in nforce2_calc_pll()
107 return NFORCE2_PLL(mul, div); in nforce2_calc_pll()
/drivers/media/i2c/
A Dccs-pll.c320 (mul & 1) && (more_mul & 1)) in __ccs_pll_calculate_vt_tree()
323 pll_fr->pll_multiplier = mul * more_mul; in __ccs_pll_calculate_vt_tree()
426 u32 mul, div; in ccs_pll_calculate_vt_tree() local
434 pll_fr->pre_pll_clk_div, mul, div); in ccs_pll_calculate_vt_tree()
437 mul, div); in ccs_pll_calculate_vt_tree()
643 op_pll_fr->pre_pll_clk_div * mul)); in ccs_pll_calculate_op()
685 mul & 1 && i & 1) in ccs_pll_calculate_op()
694 op_pll_fr->pll_multiplier = mul * i; in ccs_pll_calculate_op()
739 u32 mul, div; in ccs_pll_calculate() local
835 mul = op_sys_clk_freq_hz_sdr / i; in ccs_pll_calculate()
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A Dds90ub953.c865 unsigned long mul, div; in ub953_calc_clkout_ub953() local
873 (1 << 8) - 1, &mul, &div); in ub953_calc_clkout_ub953()
875 res = div_u64(fc_divided * mul, div); in ub953_calc_clkout_ub953()
878 *m = mul; in ub953_calc_clkout_ub953()
889 unsigned long mul, div; in ub953_calc_clkout_ub971() local
897 (1 << 8) - 1, &mul, &div); in ub953_calc_clkout_ub971()
901 *m = mul; in ub953_calc_clkout_ub971()
977 u32 mul, div; in ub953_clkout_recalc_rate() local
998 mul = ctrl0 & 0x1f; in ub953_clkout_recalc_rate()
1007 fc_rate, mul, div, rate); in ub953_clkout_recalc_rate()
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/drivers/gpu/drm/i915/display/
A Dintel_fixed.h75 static inline u32 mul_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t mul) in mul_round_up_u32_fixed16() argument
79 tmp = mul_u32_u32(val, mul.val); in mul_round_up_u32_fixed16()
87 uint_fixed_16_16_t mul) in mul_fixed16()
91 tmp = mul_u32_u32(val.val, mul.val); in mul_fixed16()
118 static inline uint_fixed_16_16_t mul_u32_fixed16(u32 val, uint_fixed_16_16_t mul) in mul_u32_fixed16() argument
122 tmp = mul_u32_u32(val, mul.val); in mul_u32_fixed16()
/drivers/net/wireless/ath/ath9k/
A Dcommon.h39 #define ATH_EP_MUL(x, mul) ((x) * (mul)) argument
47 #define ATH_EP_RND(x, mul) \ argument
48 (((x) + ((mul)/2)) / (mul))
/drivers/pwm/
A Dpwm-img.c93 unsigned long mul, output_clk_hz, input_clk_hz; in img_pwm_config() local
107 mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz); in img_pwm_config()
108 if (mul <= max_timebase) { in img_pwm_config()
110 timebase = DIV_ROUND_UP(mul, 1); in img_pwm_config()
111 } else if (mul <= max_timebase * 8) { in img_pwm_config()
113 timebase = DIV_ROUND_UP(mul, 8); in img_pwm_config()
114 } else if (mul <= max_timebase * 64) { in img_pwm_config()
116 timebase = DIV_ROUND_UP(mul, 64); in img_pwm_config()
117 } else if (mul <= max_timebase * 512) { in img_pwm_config()
119 timebase = DIV_ROUND_UP(mul, 512); in img_pwm_config()
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_afmt.c54 unsigned long div, mul; in amdgpu_afmt_calc_cts() local
70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts()
72 n *= mul; in amdgpu_afmt_calc_cts()
73 cts *= mul; in amdgpu_afmt_calc_cts()
/drivers/iio/
A Dindustrialio-gts-helper.c309 gts->itime_table[i].mul; in compute_per_time_gains()
593 if (t->sel < 0 || t->time_us < 0 || t->mul <= 0) in sanity_check_time()
628 int gain, mul, res; in iio_gts_sanity_check() local
631 mul = gts->itime_table[t].mul; in iio_gts_sanity_check()
633 if (check_mul_overflow(gain, mul, &res)) in iio_gts_sanity_check()
916 return time->mul; in iio_gts_get_int_time_gain_multiplier_by_sel()
940 int ret, mul; in iio_gts_find_gain_for_scale_using_time() local
950 mul = ret; in iio_gts_find_gain_for_scale_using_time()
1051 return gain * itime->mul; in iio_gts_get_total_gain()
1145 ret = gain_get_scale_fraction(gts->max_scale, scale, itime_new->mul, in iio_gts_find_new_gain_sel_by_old_gain_time()
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/drivers/clk/imgtec/
A Dclk-boston.c34 uint mmcmdiv, mul, cpu_div, sys_div; in clk_boston_setup() local
53 mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL); in clk_boston_setup()
56 sys_freq = mult_frac(in_freq, mul, sys_div); in clk_boston_setup()
59 cpu_freq = mult_frac(in_freq, mul, cpu_div); in clk_boston_setup()
/drivers/gpu/drm/tegra/
A Dhda.c14 unsigned int mul, div, bits, channels; in tegra_hda_parse_format() local
26 mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT; in tegra_hda_parse_format()
29 fmt->sample_rate *= (mul + 1) / (div + 1); in tegra_hda_parse_format()
A Ddsi.c45 unsigned int mul; member
482 unsigned int hact, hsw, hbp, hfp, i, mul, div; in tegra_dsi_configure() local
493 mul = state->mul; in tegra_dsi_configure()
540 hact = mode->hdisplay * mul / div; in tegra_dsi_configure()
546 hbp = (mode->htotal - mode->hsync_end) * mul / div; in tegra_dsi_configure()
565 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); in tegra_dsi_configure()
575 bytes = 1 + (mode->hdisplay / 2) * mul / div; in tegra_dsi_configure()
578 bytes = 1 + mode->hdisplay * mul / div; in tegra_dsi_configure()
597 delay = DIV_ROUND_UP(delay * mul, div * lanes); in tegra_dsi_configure()
601 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); in tegra_dsi_configure()
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/drivers/media/radio/si4713/
A Dsi4713.c935 *mul = 1; in si4713_choose_econtrol_action()
939 *mul = 1; in si4713_choose_econtrol_action()
943 *mul = 1; in si4713_choose_econtrol_action()
947 *mul = 1; in si4713_choose_econtrol_action()
951 *mul = ATTACK_TIME_UNIT; in si4713_choose_econtrol_action()
955 *mul = 10; in si4713_choose_econtrol_action()
959 *mul = 10; in si4713_choose_econtrol_action()
963 *mul = 1; in si4713_choose_econtrol_action()
1110 int mul = 0; in si4713_s_ctrl() local
1189 if (mul) { in si4713_s_ctrl()
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/drivers/clk/ralink/
A Dclk-mtmips.c550 static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) in mt7620_calc_rate() argument
555 t *= mul; in mt7620_calc_rate()
569 u32 mul; in mt7620_pll_recalc_rate() local
578 mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & in mt7620_pll_recalc_rate()
580 mul += 24; in mt7620_pll_recalc_rate()
582 mul *= 2; in mt7620_pll_recalc_rate()
589 cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]); in mt7620_pll_recalc_rate()
608 u32 mul; in mt7620_cpu_recalc_rate() local
612 mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; in mt7620_cpu_recalc_rate()
616 return mt7620_calc_rate(parent_rate, mul, div); in mt7620_cpu_recalc_rate()
/drivers/acpi/
A Dcppc_acpi.c1969 u64 mul, div; in cppc_perf_to_khz() local
1974 mul = caps->nominal_freq; in cppc_perf_to_khz()
1980 mul *= KHZ_PER_MHZ; in cppc_perf_to_khz()
1982 div64_u64(caps->nominal_perf * mul, div); in cppc_perf_to_khz()
1986 mul = max_khz; in cppc_perf_to_khz()
1990 retval = offset + div64_u64(perf * mul, div); in cppc_perf_to_khz()
2001 u64 mul, div; in cppc_khz_to_perf() local
2006 mul = caps->nominal_perf; in cppc_khz_to_perf()
2018 div64_u64(caps->nominal_freq * mul, div); in cppc_khz_to_perf()
2024 mul = caps->highest_perf; in cppc_khz_to_perf()
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