| /drivers/clk/rockchip/ |
| A D | clk-ddr.c | 19 int mux_shift; member
77 ddrclk->mux_offset) >> ddrclk->mux_shift; in rockchip_ddrclk_get_parent()
93 int mux_shift, int mux_width, in rockchip_clk_register_ddrclk() argument
127 ddrclk->mux_shift = mux_shift; in rockchip_clk_register_ddrclk()
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| A D | clk.h | 689 u8 mux_shift; member
716 .mux_shift = ms, \
737 .mux_shift = ms, \
796 .mux_shift = ms, \
814 .mux_shift = ms, \
833 .mux_shift = ms, \
921 .mux_shift = s, \
936 .mux_shift = s, \
952 .mux_shift = s, \
1102 .mux_shift = ms, \
[all …]
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| A D | clk.c | 42 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, in rockchip_clk_register_branch() argument
63 mux->shift = mux_shift; in rockchip_clk_register_branch()
270 frac_mux->shift = child->mux_shift; in rockchip_clk_register_frac_branch()
532 list->mux_shift, list->mux_width, in rockchip_clk_register_branches()
540 list->mux_shift, list->mux_width, in rockchip_clk_register_branches()
547 list->mux_shift, list->mux_width, in rockchip_clk_register_branches()
579 list->mux_shift, list->mux_width, in rockchip_clk_register_branches()
604 list->mux_shift, in rockchip_clk_register_branches()
649 list->muxdiv_offset, list->mux_shift, in rockchip_clk_register_branches()
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| A D | clk-half-divider.c | 161 int muxdiv_offset, u8 mux_shift, in rockchip_clk_register_halfdiv() argument
182 mux->shift = mux_shift; in rockchip_clk_register_halfdiv()
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| /drivers/clk/mediatek/ |
| A D | clk-mux.c | 90 val = (val >> mux->data->mux_shift) & mask; in mtk_clk_mux_get_parent()
122 val = (orig & ~(mask << mux->data->mux_shift)) in mtk_clk_mux_set_parent_setclr_lock()
123 | (index << mux->data->mux_shift); in mtk_clk_mux_set_parent_setclr_lock()
127 mask << mux->data->mux_shift); in mtk_clk_mux_set_parent_setclr_lock()
129 index << mux->data->mux_shift); in mtk_clk_mux_set_parent_setclr_lock()
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| A D | clk-mtk.h | 100 signed char mux_shift; member
117 .mux_shift = _shift, \
153 .mux_shift = _shift, \
172 .mux_shift = -1, \
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| A D | clk-mux.h | 32 u8 mux_shift; member
51 .mux_shift = _shift, \
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| A D | clk-cpumux.c | 80 cpumux->shift = mux->mux_shift; in mtk_clk_register_cpumux()
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| A D | clk-mtk.c | 232 if (mc->mux_shift >= 0) { in mtk_clk_register_composite()
239 mux->shift = mc->mux_shift; in mtk_clk_register_composite()
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| /drivers/clk/ |
| A D | clk-bm1880.c | 119 s8 mux_shift; member
156 .mux_shift = -1, \
170 .mux_shift = _mux_shift, \
768 if (clks->mux_shift >= 0) { in bm1880_clk_register_composite()
775 mux->shift = clks->mux_shift; in bm1880_clk_register_composite()
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| /drivers/clk/x86/ |
| A D | clk-cgu.h | 177 u8 mux_shift; member
213 .mux_shift = _shift, \
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| A D | clk-cgu.c | 86 u8 shift = list->mux_shift; in lgm_clk_register_mux()
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| /drivers/pinctrl/ |
| A D | pinctrl-pistachio.c | 90 int mux_shift; member
645 .mux_shift = -1, \
659 .mux_shift = -1, \
673 .mux_shift = _shift, \
966 val &= ~(pg->mux_mask << pg->mux_shift); in pistachio_pinmux_enable()
967 val |= i << pg->mux_shift; in pistachio_pinmux_enable()
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| A D | pinctrl-zynq.c | 74 u8 mux_shift; member
772 .mux_shift = shift, \
913 reg |= pgrp->pins[0] << func->mux_shift; in zynq_pinmux_set_mux()
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| A D | pinctrl-bm1880.c | 71 u8 mux_shift; member
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| /drivers/pinctrl/freescale/ |
| A D | pinctrl-imx.h | 92 u8 mux_shift; member
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| A D | pinctrl-imx8ulp.c | 248 .mux_shift = BP_MUX_MODE,
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| A D | pinctrl-imx7ulp.c | 289 .mux_shift = BP_MUX_MODE,
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| A D | pinctrl-vf610.c | 322 .mux_shift = 20,
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| A D | pinctrl-imx.c | 187 reg |= (pin_mmio->mux_mode << info->mux_shift); in imx_pmx_set_one_pin_mmio()
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| /drivers/soc/tegra/ |
| A D | pmc.c | 206 u32 mux_shift; member
225 u8 mux_shift; member
247 .mux_shift = 6,
255 .mux_shift = 14,
263 .mux_shift = 22,
2557 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2569 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); in pmc_clk_mux_set_parent()
2570 val |= index << clk->mux_shift; in pmc_clk_mux_set_parent()
2643 pmc_clk->mux_shift = data->mux_shift; in tegra_pmc_clk_out_register()
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