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Searched refs:mvdd_control (Results 1 – 24 of 24) sorted by relevance

/drivers/gpu/drm/radeon/
A Dcypress_dpm.c661 if (!pi->mvdd_control) { in cypress_populate_mvdd_value()
1584 pi->mvdd_control = false; in cypress_get_mvdd_configuration()
1599 pi->mvdd_control = false; in cypress_get_mvdd_configuration()
1607 pi->mvdd_control = false; in cypress_get_mvdd_configuration()
1828 if (pi->mvdd_control) { in cypress_dpm_enable()
2077 pi->mvdd_control = in cypress_dpm_init()
A Dci_dpm.h195 u32 mvdd_control; member
A Drv770_dpm.h83 bool mvdd_control; member
A Drv770_dpm.c598 if (!pi->mvdd_control) { in rv770_populate_mvdd_value()
1149 if (pi->mvdd_control) { in rv770_populate_smc_mvdd_table()
1319 pi->mvdd_control = false; in rv770_get_mvdd_configuration()
1327 pi->mvdd_control = false; in rv770_get_mvdd_configuration()
1919 if (pi->mvdd_control) { in rv770_dpm_enable()
2393 pi->mvdd_control = in rv770_dpm_init()
A Dsi_dpm.c3939 if (pi->mvdd_control) { in si_construct_voltage_tables()
3944 pi->mvdd_control = false; in si_construct_voltage_tables()
3949 pi->mvdd_control = false; in si_construct_voltage_tables()
4072 if (pi->mvdd_control) { in si_populate_mvdd_value()
4294 if (pi->mvdd_control) in si_populate_initial_mvdd_value()
6297 if (pi->mvdd_control) in si_dpm_enable()
6950 pi->mvdd_control = in si_dpm_init()
A Dci_dpm.c2131 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2137 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2232 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2269 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
5831 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5848 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5850 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
A Dbtc_dpm.c2374 if (pi->mvdd_control) { in btc_dpm_enable()
2608 pi->mvdd_control = in btc_dpm_init()
A Dni_dpm.c1327 if (!pi->mvdd_control) { in ni_populate_mvdd_value()
4143 pi->mvdd_control = in ni_dpm_init()
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dvegam_smumgr.c454 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in vegam_populate_smc_mvdd_table()
632 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in vegam_get_dependency_volt_by_clk()
661 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in vegam_get_dependency_volt_by_clk()
1093 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in vegam_populate_mvdd_value()
1699 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { in vegam_populate_vr_config()
1714 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in vegam_populate_vr_config()
A Dpolaris10_smumgr.c385 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in polaris10_get_dependency_volt_by_clk()
412 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in polaris10_get_dependency_volt_by_clk()
670 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in polaris10_populate_smc_mvdd_table()
1260 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in polaris10_populate_mvdd_value()
1337 if (!((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) || in polaris10_populate_smc_acpi_level()
1745 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { in polaris10_populate_vr_config()
1755 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in polaris10_populate_vr_config()
A Dfiji_smumgr.c384 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in fiji_get_dependency_volt_by_clk()
409 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in fiji_get_dependency_volt_by_clk()
1279 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in fiji_populate_mvdd_value()
1390 if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) || in fiji_populate_smc_acpi_level()
1847 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { in fiji_populate_vr_config()
1850 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in fiji_populate_vr_config()
A Dtonga_smumgr.c372 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in tonga_populate_smc_mvdd_table()
994 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) in tonga_populate_single_memory_level()
1151 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in tonga_populate_mvdd_value()
1789 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in tonga_populate_vr_config()
A Diceland_smumgr.c682 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) in iceland_populate_smc_mvdd_table()
1402 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in iceland_populate_mvdd_value()
1920 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) in iceland_populate_smc_svi2_config()
A Dci_smumgr.c912 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in ci_populate_smc_mvdd_table()
1357 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in ci_populate_mvdd_value()
1934 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in ci_populate_vr_config()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu7_hwmgr.h241 uint32_t mvdd_control; member
A Dvega10_hwmgr.h321 uint32_t mvdd_control; member
A Dvega12_hwmgr.h323 uint32_t mvdd_control; member
A Dvega20_hwmgr.h447 uint32_t mvdd_control; member
A Dsmu7_hwmgr.c324 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in smu7_construct_voltage_tables()
331 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { in smu7_construct_voltage_tables()
1830 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE; in smu7_init_dpm_defaults()
1893 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; in smu7_init_dpm_defaults()
1896 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; in smu7_init_dpm_defaults()
1913 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) in smu7_init_dpm_defaults()
A Dvega10_hwmgr.c849 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE; in vega10_hwmgr_backend_init()
879 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; in vega10_hwmgr_backend_init()
1177 if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || in vega10_construct_voltage_tables()
1178 data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) { in vega10_construct_voltage_tables()
A Dvega12_hwmgr.c411 data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE; in vega12_hwmgr_backend_init()
A Dvega20_hwmgr.c455 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE; in vega20_hwmgr_backend_init()
/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dsi_dpm.h539 bool mvdd_control; member
A Dsi_dpm.c4479 if (pi->mvdd_control) { in si_construct_voltage_tables()
4484 pi->mvdd_control = false; in si_construct_voltage_tables()
4489 pi->mvdd_control = false; in si_construct_voltage_tables()
4612 if (pi->mvdd_control) { in si_populate_mvdd_value()
4838 if (pi->mvdd_control) in si_populate_initial_mvdd_value()
6842 if (pi->mvdd_control) in si_dpm_enable()
7468 pi->mvdd_control = in si_dpm_init()

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