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/drivers/media/pci/solo6x10/
A Dsolo6x10-regs.h41 #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) argument
49 #define SOLO_VCLK_SELECT(n) ((n)<<20) argument
61 #define SOLO_IRQ_P2M(n) BIT((n) + 17) argument
73 #define SOLO_IRQ_UART(n) BIT((n) + 4) argument
125 #define SOLO_P2M_PCI_INC(n) ((n)<<20) argument
126 #define SOLO_P2M_REPEAT(n) ((n)<<10) argument
179 #define SOLO_VI_V_STOP(n) ((n)<<0) argument
267 #define SOLO_VO_H_STOP(n) ((n)<<0) argument
272 #define SOLO_VO_V_STOP(n) ((n)<<0) argument
278 #define SOLO_VO_H_LEN(n) ((n)<<11) argument
[all …]
/drivers/staging/media/starfive/camss/
A Dstf-isp.h32 #define CSI_INTS(n) ((n) << 16) argument
33 #define CSI_SHA_M(n) ((n) << 0) argument
56 #define SMY13(n) ((n) << 14) argument
57 #define SMY12(n) ((n) << 12) argument
58 #define SMY11(n) ((n) << 10) argument
59 #define SMY10(n) ((n) << 8) argument
60 #define SMY3(n) ((n) << 6) argument
61 #define SMY2(n) ((n) << 4) argument
62 #define SMY1(n) ((n) << 2) argument
63 #define SMY0(n) ((n) << 0) argument
[all …]
/drivers/media/common/siano/
A Dsmsdvb-debugfs.c37 int n = 0; in smsdvb_print_dvb_stats() local
51 n += sysfs_emit_at(buf, n, "SNR = %d\n", p->SNR); in smsdvb_print_dvb_stats()
52 n += sysfs_emit_at(buf, n, "ber = %d\n", p->ber); in smsdvb_print_dvb_stats()
53 n += sysfs_emit_at(buf, n, "FIB_CRC = %d\n", p->FIB_CRC); in smsdvb_print_dvb_stats()
54 n += sysfs_emit_at(buf, n, "ts_per = %d\n", p->ts_per); in smsdvb_print_dvb_stats()
55 n += sysfs_emit_at(buf, n, "MFER = %d\n", p->MFER); in smsdvb_print_dvb_stats()
56 n += sysfs_emit_at(buf, n, "RSSI = %d\n", p->RSSI); in smsdvb_print_dvb_stats()
116 n += sysfs_emit_at(buf, n, "SNR = %d dB\t\t", p->SNR); in smsdvb_print_isdb_stats()
135 n += sysfs_emit_at(buf, n, "\nLayer %d\n", i); in smsdvb_print_isdb_stats()
141 n += sysfs_emit_at(buf, n, "ber_bit_count = %-5d\n", in smsdvb_print_isdb_stats()
[all …]
/drivers/media/platform/nxp/imx8-isi/
A Dimx8-isi-regs.h17 #define CHNL_CTRL_CHAIN_BUF(n) ((n) << 25) argument
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16) argument
24 #define CHNL_CTRL_MIPI_VC_ID(n) ((n) << 6) argument
26 #define CHNL_CTRL_SRC_TYPE(n) ((n) << 4) argument
30 #define CHNL_CTRL_SRC_INPUT(n) ((n) << 0) argument
35 #define CHNL_IMG_CTRL_FORMAT(n) ((n) << 24) argument
195 #define CHNL_CROP_ULC_X(n) ((n) << 16) argument
197 #define CHNL_CROP_ULC_Y(n) ((n) << 0) argument
202 #define CHNL_CROP_LRC_X(n) ((n) << 16) argument
204 #define CHNL_CROP_LRC_Y(n) ((n) << 0) argument
[all …]
/drivers/media/cec/core/
A Dcec-notifier.c66 n = kzalloc(sizeof(*n), GFP_KERNEL); in cec_notifier_get_conn()
67 if (!n) in cec_notifier_get_conn()
85 return n; in cec_notifier_get_conn()
95 kfree(n); in cec_notifier_release()
111 if (!n) in cec_notifier_conn_register()
119 memset(&n->conn_info, 0, sizeof(n->conn_info)); in cec_notifier_conn_register()
126 return n; in cec_notifier_conn_register()
132 if (!n) in cec_notifier_conn_unregister()
136 memset(&n->conn_info, 0, sizeof(n->conn_info)); in cec_notifier_conn_unregister()
158 if (!n) in cec_notifier_cec_adap_register()
[all …]
/drivers/gpu/drm/exynos/
A Dregs-decon5433.h12 #define DECON_WINCONx(n) (0x0020 + ((n) * 4)) argument
13 #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4)) argument
15 #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20)) argument
16 #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20)) argument
17 #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20)) argument
18 #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20)) argument
33 #define DECON_WINxMAP(n) (0x0270 + ((n) * 4)) argument
220 #define BLENDERQ_Q_FUNC_F(n) (n << 18) argument
221 #define BLENDERQ_P_FUNC_F(n) (n << 12) argument
222 #define BLENDERQ_B_FUNC_F(n) (n << 6) argument
[all …]
/drivers/net/ethernet/intel/igc/
A Digc_dump.c53 for (n = 0; n < 4; n++) in igc_regdump()
57 for (n = 0; n < 4; n++) in igc_regdump()
61 for (n = 0; n < 4; n++) in igc_regdump()
65 for (n = 0; n < 4; n++) in igc_regdump()
69 for (n = 0; n < 4; n++) in igc_regdump()
73 for (n = 0; n < 4; n++) in igc_regdump()
77 for (n = 0; n < 4; n++) in igc_regdump()
81 for (n = 0; n < 4; n++) in igc_regdump()
85 for (n = 0; n < 4; n++) in igc_regdump()
89 for (n = 0; n < 4; n++) in igc_regdump()
[all …]
/drivers/usb/dwc3/
A Dcore.h253 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) argument
263 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) argument
270 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) argument
294 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) argument
305 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) argument
319 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) argument
321 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) argument
460 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) argument
593 #define DWC3_DALEPENA_EP(n) BIT(n) argument
919 #define DWC3_MODE(n) ((n) & 0x7) argument
[all …]
/drivers/phy/allwinner/
A Dphy-sun6i-mipi-dphy.c21 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4) argument
38 #define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff) argument
44 #define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff) argument
47 #define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff) argument
53 #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff) argument
66 #define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff) argument
80 #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12) argument
83 #define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2) argument
111 #define SUN6I_DPHY_ANA4_REG_IB(n) (((n) & 3) << 25) argument
121 #define SUN6I_DPHY_ANA4_REG_TXPUSD(n) ((n) & 3) argument
[all …]
/drivers/clk/at91/
A Dsam9x60.c83 char *n; member
100 char *n; member
104 { .n = "pioA_clk", .id = 2, },
105 { .n = "pioB_clk", .id = 3, },
106 { .n = "pioC_clk", .id = 4, },
107 { .n = "flex0_clk", .id = 5, },
108 { .n = "flex1_clk", .id = 6, },
109 { .n = "flex2_clk", .id = 7, },
156 char *n; member
346 sam9x60_periphck[i].n, in sam9x60_pmc_setup()
[all …]
A Dsama5d4.c40 char *n; member
60 char *n; member
63 { .n = "pioD_clk", .id = 5 },
66 { .n = "icm_clk", .id = 9 },
67 { .n = "aes_clk", .id = 12 },
68 { .n = "tdes_clk", .id = 14 },
69 { .n = "sha_clk", .id = 15 },
92 { .n = "pwm_clk", .id = 43 },
93 { .n = "adc_clk", .id = 44 },
104 { .n = "smd_clk", .id = 61 },
[all …]
A Dat91sam9260.c11 char *n; member
17 char *n; member
83 { .n = "pioA_clk", .id = 2 },
84 { .n = "pioB_clk", .id = 3 },
85 { .n = "pioC_clk", .id = 4 },
86 { .n = "adc_clk", .id = 5 },
87 { .n = "usart0_clk", .id = 6 },
88 { .n = "usart1_clk", .id = 7 },
89 { .n = "usart2_clk", .id = 8 },
90 { .n = "mci0_clk", .id = 9 },
[all …]
A Dsama5d2.c41 char *n; member
61 char *n; member
67 { .n = "matrix1_clk", .id = 14, },
68 { .n = "hsmc_clk", .id = 17, },
104 char *n; member
108 { .n = "dma0_clk", .id = 6, },
109 { .n = "dma1_clk", .id = 7, },
128 char *n; member
326 sama5d2_periphck[i].n, in sama5d2_pmc_setup()
340 sama5d2_periph32ck[i].n, in sama5d2_pmc_setup()
[all …]
A Dsam9x7.c194 const char *n; member
338 char *n; member
360 char *n; member
431 const char *n; member
549 .n = "tcb0_gclk",
558 .n = "adc_gclk",
567 .n = "lcd_gclk",
625 .n = "i2s_gclk",
635 .n = "qspi_gclk",
664 .n = "tcb1_gclk",
[all …]
A Dsama5d3.c41 char *n; member
61 char *n; member
66 { .n = "dbgu_clk", .id = 2, },
67 { .n = "hsmc_clk", .id = 5, },
68 { .n = "pioA_clk", .id = 6, },
69 { .n = "pioB_clk", .id = 7, },
70 { .n = "pioC_clk", .id = 8, },
71 { .n = "pioD_clk", .id = 9, },
72 { .n = "pioE_clk", .id = 10, },
89 { .n = "pwm_clk", .id = 28, },
[all …]
A Dsama7d65.c192 const char *n; member
449 const char *n; member
463 { .n = "mck1",
472 { .n = "mck2",
480 { .n = "mck3",
489 { .n = "mck4",
497 { .n = "mck5",
506 { .n = "mck6",
514 { .n = "mck7",
521 { .n = "mck8",
[all …]
/drivers/media/platform/renesas/vsp1/
A Dvsp1_regs.h17 #define VI6_CMD(n) (0x0000 + (n) * 4) argument
28 #define VI6_SRESET_SRTS(n) BIT(n) argument
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8) argument
47 #define VI6_DISP_IRQ_ENB_LNEE(n) BIT(n) argument
52 #define VI6_DISP_IRQ_STA_LNE(n) BIT(n) argument
417 #define VI6_DPR_NODE_RPF(n) (n) argument
422 #define VI6_DPR_NODE_BRU_IN(n) (((n) <= 3) ? 23 + (n) : 49) argument
633 #define VI6_BRU_CTRL_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20) argument
636 #define VI6_BRU_CTRL_SRCSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 16) argument
644 #define VI6_BRU_BLD(n) (0x0014 + (n) * 8 + ((n) <= 3 ? 0 : 4)) argument
[all …]
/drivers/gpu/drm/renesas/rcar-du/
A Drcar_du_regs.h72 #define DSSR_DFB(n) (1 << ((n)+15)) argument
78 #define DSSR_ADC(n) (1 << ((n)-1)) argument
86 #define DSRCR_ADCL(n) (1 << ((n)-1)) argument
95 #define DIER_ADCE(n) (1 << ((n)-1)) argument
104 #define DPPR_DPE(n) (1 << ((n)*4-1)) argument
106 #define DPPR_DPS_SHIFT(n) (((n)-1)*4) argument
289 #define DPLLCR_N(n) ((n) << 5) argument
290 #define DPLLCR_M(n) ((n) << 3) argument
298 #define DPLLC2R_M(n) ((n) << 8) argument
299 #define DPLLC2R_FDPLL(n) ((n) << 0) argument
[all …]
/drivers/net/ethernet/meta/fbnic/
A Dfbnic_csr.h212 #define FBNIC_INTR_STATUS(n) (0x00000 + (n)) /* 0x00000 + 4*n */ argument
214 #define FBNIC_INTR_MASK(n) (0x00008 + (n)) /* 0x00020 + 4*n */ argument
216 #define FBNIC_INTR_SET(n) (0x00010 + (n)) /* 0x00040 + 4*n */ argument
218 #define FBNIC_INTR_CLEAR(n) (0x00018 + (n)) /* 0x00060 + 4*n */ argument
260 #define FBNIC_QM_TWQ_IDLE(n) (0x00800 + (n)) /* 0x02000 + 4*n */ argument
283 #define FBNIC_QM_TCQ_IDLE(n) (0x00821 + (n)) /* 0x02084 + 4*n */ argument
288 #define FBNIC_QM_TQS_IDLE(n) (0x00830 + (n)) /* 0x020c0 + 4*n */ argument
291 #define FBNIC_QM_TDE_IDLE(n) (0x00853 + (n)) /* 0x0214c + 4*n */ argument
313 #define FBNIC_QM_RCQ_IDLE(n) (0x00c00 + (n)) /* 0x03000 + 4*n */ argument
318 #define FBNIC_QM_HPQ_IDLE(n) (0x00c0f + (n)) /* 0x0303c + 4*n */ argument
[all …]
/drivers/gpu/drm/omapdrm/dss/
A Ddispc.h37 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
39 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
41 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
43 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
45 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
47 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \ argument
57 #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \ argument
65 #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \ argument
67 #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \ argument
71 #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \ argument
[all …]
/drivers/video/fbdev/omap2/omapfb/dss/
A Ddispc.h34 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
36 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
38 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
40 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
42 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
44 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \ argument
54 #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \ argument
62 #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \ argument
64 #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \ argument
68 #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \ argument
[all …]
/drivers/vhost/
A Dtest.c102 handle_vq(n); in handle_vq_kick()
107 struct vhost_test *n = kmalloc(sizeof *n, GFP_KERNEL); in vhost_test_open() local
111 if (!n) in vhost_test_open()
115 kfree(n); in vhost_test_open()
119 dev = &n->dev; in vhost_test_open()
125 f->private_data = n; in vhost_test_open()
144 *privatep = vhost_test_stop_vq(n, n->vqs + VHOST_TEST_VQ); in vhost_test_stop()
158 vhost_test_flush(n); in vhost_test_release()
161 kfree(n->dev.vqs); in vhost_test_release()
162 kfree(n); in vhost_test_release()
[all …]
/drivers/crypto/inside-secure/
A Dsafexcel.h40 #define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3) argument
41 #define EIP206_OPT_OCE_TYPE(n) ((n>>10)&3) argument
230 #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n) argument
236 #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n) argument
246 #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24) argument
280 #define EIP197_CDR_IRQ(n) BIT((n) * 2) argument
281 #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1) argument
305 #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) argument
308 #define EIP197_G_IRQ_PE(n) BIT((n) + 20) argument
357 #define EIP197_CONTEXT_SIZE(n) (n) argument
[all …]
/drivers/gpu/drm/mxsfb/
A Dlcdif_regs.h150 #define DISP_SIZE_DELTA_Y(n) (((n) & 0xffff) << 16) argument
152 #define DISP_SIZE_DELTA_X(n) ((n) & 0xffff) argument
155 #define HSYN_PARA_BP_H(n) (((n) & 0xffff) << 16) argument
157 #define HSYN_PARA_FP_H(n) ((n) & 0xffff) argument
160 #define VSYN_PARA_BP_V(n) (((n) & 0xffff) << 16) argument
162 #define VSYN_PARA_FP_V(n) ((n) & 0xffff) argument
167 #define VSYN_HSYN_WIDTH_PW_H(n) ((n) & 0xffff) argument
190 #define CTRLDESCL0_1_WIDTH(n) ((n) & 0xffff) argument
197 #define CTRLDESCL0_3_PITCH(n) ((n) & 0xffff) argument
200 #define CTRLDESCL_HIGH0_4_ADDR_HIGH(n) ((n) & 0xf) argument
[all …]
/drivers/media/platform/qcom/camss/
A Dcamss-vfe-480.c24 return vfe_is_lite(vfe) ? BIT(n) : BIT(1 + (n)); in reg_update_rdi()
31 #define VFE_IRQ_MASK(n) ((vfe_is_lite(vfe) ? 0x28 : 0x3c) + (n) * 4) argument
34 #define VFE_IRQ_CLEAR(n) ((vfe_is_lite(vfe) ? 0x34 : 0x48) + (n) * 4) argument
44 #define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4) argument
47 return vfe_is_lite(vfe) ? BIT(n) : BIT(3 + (n)); in bus_irq_mask_0_rdi_rup()
53 return vfe_is_lite(vfe) ? BIT(4 + (n)) : BIT(6 + (n)); in bus_irq_mask_0_comp_done()
57 #define VFE_BUS_IRQ_CLEAR(n) (BUS_REG_BASE + 0x20 + (n) * 4) argument
58 #define VFE_BUS_IRQ_STATUS(n) (BUS_REG_BASE + 0x28 + (n) * 4) argument
61 #define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) argument
88 #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0 : 23) + (n)) argument
[all …]

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