| /drivers/gpu/drm/amd/amdgpu/ |
| A D | umc_v8_10.c | 71 uint32_t node_inst, in get_umc_v8_10_reg_offset() argument
76 UMC_8_NODE_DIST * node_inst; in get_umc_v8_10_reg_offset()
80 uint32_t node_inst, uint32_t umc_inst, in umc_v8_10_clear_error_count_per_channel() argument
144 uint32_t node_inst, uint32_t umc_inst, in umc_v8_10_query_ecc_error_count() argument
245 uint32_t node_inst, uint32_t umc_inst, in umc_v8_10_query_error_address() argument
278 ch_inst, umc_inst, node_inst, mc_umc_status); in umc_v8_10_query_error_address()
295 uint32_t node_inst, uint32_t umc_inst, in umc_v8_10_err_cnt_init_per_channel() argument
380 uint32_t node_inst, uint32_t umc_inst, in umc_v8_10_ecc_info_query_ecc_error_count() argument
386 node_inst, umc_inst, ch_inst, in umc_v8_10_ecc_info_query_ecc_error_count()
389 node_inst, umc_inst, ch_inst, in umc_v8_10_ecc_info_query_ecc_error_count()
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| A D | umc_v12_0.c | 35 uint32_t node_inst, in get_umc_v12_0_reg_offset() argument
46 UMC_V12_0_NODE_DIST * node_inst + cross_node_offset; in get_umc_v12_0_reg_offset()
50 uint32_t node_inst, uint32_t umc_inst, in umc_v12_0_reset_error_count_per_channel() argument
55 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); in umc_v12_0_reset_error_count_per_channel()
138 uint32_t node_inst, uint32_t umc_inst, in umc_v12_0_query_error_count() argument
148 .die_id = node_inst, in umc_v12_0_query_error_count()
152 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); in umc_v12_0_query_error_count()
327 uint32_t node_inst, uint32_t umc_inst, in umc_v12_0_query_error_address() argument
336 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); in umc_v12_0_query_error_address()
373 addr_in.ma.node_inst = node_inst; in umc_v12_0_query_error_address()
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| A D | amdgpu_umc.h | 49 #define LOOP_UMC_NODE_INST(node_inst) \ argument
50 for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
52 #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \ argument
53 LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
93 typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,
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| A D | amdgpu_umc.c | 394 uint32_t node_inst; in amdgpu_umc_loop_all_aid() local
410 node_inst = umc_node_inst / adev->umc.umc_inst_num; in amdgpu_umc_loop_all_aid()
415 node_inst, umc_inst, ch_inst); in amdgpu_umc_loop_all_aid()
416 ret = func(adev, node_inst, umc_inst, ch_inst, data); in amdgpu_umc_loop_all_aid()
420 node_inst, umc_inst, ch_inst, ret); in amdgpu_umc_loop_all_aid()
432 uint32_t node_inst = 0; in amdgpu_umc_loop_channels() local
441 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) { in amdgpu_umc_loop_channels()
442 ret = func(adev, node_inst, umc_inst, ch_inst, data); in amdgpu_umc_loop_channels()
445 node_inst, umc_inst, ch_inst, ret); in amdgpu_umc_loop_channels()
551 addr_in.ma.node_inst = node; in amdgpu_umc_mca_to_addr()
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| A D | umc_v8_14.c | 38 uint32_t node_inst, uint32_t umc_inst, in umc_v8_14_clear_error_count_per_channel() argument
93 uint32_t node_inst, uint32_t umc_inst, in umc_v8_14_query_error_count_per_channel() argument
120 uint32_t node_inst, uint32_t umc_inst, in umc_v8_14_err_cnt_init_per_channel() argument
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| A D | umc_v6_7.c | 164 uint32_t node_inst, uint32_t umc_inst, in umc_v6_7_ecc_info_querry_ecc_error_count() argument
223 uint32_t node_inst, uint32_t umc_inst, in umc_v6_7_ecc_info_query_error_address() argument
362 uint32_t node_inst, uint32_t umc_inst, in umc_v6_7_reset_error_count_per_channel() argument
413 uint32_t node_inst, uint32_t umc_inst, in umc_v6_7_query_ecc_error_count() argument
442 uint32_t node_inst, uint32_t umc_inst, in umc_v6_7_query_error_address() argument
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| A D | ta_ras_if.h | 164 uint32_t node_inst; member
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| A D | amdgpu_ras.c | 2762 addr_in.ma.node_inst = TA_RAS_INV_NODE; in amdgpu_ras_mca2pa_by_idx()
2798 addr_in.ma.node_inst = die_id; in amdgpu_ras_mca2pa()
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