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Searched refs:num_banks (Results 1 – 25 of 81) sorted by relevance

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/drivers/crypto/intel/qat/qat_common/
A Dadf_isr.c25 u32 msix_num_entries = hw_data->num_banks + 1; in adf_enable_msix()
183 int clust_irq = hw_data->num_banks; in adf_free_irqs()
187 for (i = 0; i < hw_data->num_banks; i++) { in adf_free_irqs()
208 int clust_irq = hw_data->num_banks; in adf_request_irqs()
214 for (i = 0; i < hw_data->num_banks; i++) { in adf_request_irqs()
238 cpu = ((accel_dev->accel_id * hw_data->num_banks) + in adf_request_irqs()
278 msix_num_entries += hw_data->num_banks; in adf_isr_alloc_msix_vectors_data()
302 for (i = 0; i < hw_data->num_banks; i++) in adf_setup_bh()
315 for (i = 0; i < hw_data->num_banks; i++) { in adf_cleanup_bh()
A Dadf_transport.c479 u32 num_banks = 0; in adf_init_etr_data() local
487 num_banks = GET_MAX_BANKS(accel_dev); in adf_init_etr_data()
488 size = num_banks * sizeof(struct adf_etr_bank_data); in adf_init_etr_data()
503 for (i = 0; i < num_banks; i++) { in adf_init_etr_data()
546 u32 i, num_banks = GET_MAX_BANKS(accel_dev); in adf_cleanup_etr_handles() local
548 for (i = 0; i < num_banks; i++) in adf_cleanup_etr_handles()
A Dadf_bank_state.c194 if (bank_number >= hw_data->num_banks || !state) in adf_bank_state_save()
225 if (bank_number >= hw_data->num_banks || !state) in adf_bank_state_restore()
/drivers/hwspinlock/
A Dsun6i_hwspinlock.c96 u32 num_banks; in sun6i_hwspinlock_probe() local
146 num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28; in sun6i_hwspinlock_probe()
147 switch (num_banks) { in sun6i_hwspinlock_probe()
149 priv->nlocks = 1 << (4 + num_banks); in sun6i_hwspinlock_probe()
153 dev_err(&pdev->dev, "unsupported hwspinlock setup (%d)\n", num_banks); in sun6i_hwspinlock_probe()
/drivers/nvmem/
A Dnintendo-otp.c35 unsigned int num_banks; member
40 .num_banks = 1,
45 .num_banks = 8,
101 config.size = data->num_banks * BANK_SIZE; in nintendo_otp_probe()
/drivers/mtd/nand/raw/ingenic/
A Dingenic_nand_drv.c47 unsigned int num_banks; member
49 struct ingenic_nand_cs cs[] __counted_by(num_banks);
446 if (num_chips > nfc->num_banks) { in ingenic_nand_init_chips()
448 num_chips, nfc->num_banks); in ingenic_nand_init_chips()
469 unsigned int num_banks; in ingenic_nand_probe() local
473 num_banks = jz4780_nemc_num_banks(dev); in ingenic_nand_probe()
474 if (num_banks == 0) { in ingenic_nand_probe()
479 nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL); in ingenic_nand_probe()
496 nfc->num_banks = num_banks; in ingenic_nand_probe()
/drivers/gpio/
A Dgpio-brcmstb.c362 int num_banks = in brcmstb_gpio_sanity_check_banks() local
365 if (res_num_banks != num_banks) { in brcmstb_gpio_sanity_check_banks()
367 res_num_banks, num_banks); in brcmstb_gpio_sanity_check_banks()
594 int num_banks = 0; in brcmstb_gpio_probe() local
646 num_banks); in brcmstb_gpio_probe()
647 num_banks++; in brcmstb_gpio_probe()
659 bank->id = num_banks; in brcmstb_gpio_probe()
719 num_banks++; in brcmstb_gpio_probe()
A Dgpio-tegra186.c105 unsigned int num_banks; member
804 if (gpio->num_irq > gpio->num_banks) { in tegra186_gpio_irqs_per_bank()
805 if (gpio->num_irq % gpio->num_banks != 0) in tegra186_gpio_irqs_per_bank()
809 if (gpio->num_irq < gpio->num_banks) in tegra186_gpio_irqs_per_bank()
821 gpio->num_irq, gpio->num_banks); in tegra186_gpio_irqs_per_bank()
845 if (gpio->soc->ports[i].bank > gpio->num_banks) in tegra186_gpio_probe()
846 gpio->num_banks = gpio->soc->ports[i].bank; in tegra186_gpio_probe()
848 gpio->num_banks++; in tegra186_gpio_probe()
957 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, in tegra186_gpio_probe()
962 for (i = 0; i < gpio->num_banks; i++) in tegra186_gpio_probe()
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A Dgpio-stmpe.c186 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); in stmpe_gpio_irq_sync_unlock() local
225 for (j = 0; j < num_banks; j++) { in stmpe_gpio_irq_sync_unlock()
395 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); in stmpe_gpio_irq() local
413 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); in stmpe_gpio_irq()
417 for (i = 0; i < num_banks; i++) { in stmpe_gpio_irq()
419 num_banks - i - 1; in stmpe_gpio_irq()
A Dgpio-eic-sprd.c618 u16 num_banks = 0; in sprd_eic_probe() local
653 num_banks++; in sprd_eic_probe()
657 sprd_eic->chip.ngpio = num_banks * SPRD_EIC_PER_BANK_NR; in sprd_eic_probe()
/drivers/thermal/mediatek/
A Dauxadc_thermal.c312 s32 num_banks; member
486 .num_banks = MT8173_NUM_ZONES,
526 .num_banks = 1,
557 .num_banks = MT8365_NUM_BANKS,
591 .num_banks = 1,
616 .num_banks = MT7622_NUM_ZONES,
651 .num_banks = MT8183_NUM_ZONES,
676 .num_banks = MT7986_NUM_ZONES,
854 for (i = 0; i < mt->conf->num_banks; i++) { in mtk_read_temp()
1284 for (i = 0; i < mt->conf->num_banks; i++) in mtk_thermal_probe()
/drivers/leds/
A Dleds-lm3697.c90 int num_banks; member
92 struct lm3697_led leds[] __counted_by(num_banks);
193 for (i = 0; i < priv->num_banks; i++) { in lm3697_init()
318 led->num_banks = count; in lm3697_probe()
/drivers/soc/qcom/
A Docmem.c298 int i, j, ret, num_banks; in ocmem_dev_probe() local
366 num_banks = ocmem->num_ports / 2; in ocmem_dev_probe()
367 region_size = ocmem->config->macro_size * num_banks; in ocmem_dev_probe()
383 if (WARN_ON(num_banks > ARRAY_SIZE(region->macro_state))) { in ocmem_dev_probe()
389 region->num_macros = num_banks; in ocmem_dev_probe()
A Dllcc-qcom.c152 u32 num_banks; member
3523 .num_banks = 4,
3580 .num_banks = 2,
3591 .num_banks = 2,
4249 attr3_val /= drv_data->num_banks; in _qcom_llcc_cfg_program_v6()
4425 u32 num_banks; in qcom_llcc_probe() local
4463 if (cfg->num_banks) { in qcom_llcc_probe()
4464 num_banks = cfg->num_banks; in qcom_llcc_probe()
4470 num_banks &= LLCC_LB_CNT_MASK; in qcom_llcc_probe()
4471 num_banks >>= LLCC_LB_CNT_SHIFT; in qcom_llcc_probe()
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/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_socbb.h68 uint32_t num_banks; member
/drivers/gpu/drm/amd/display/dc/dml/dcn10/
A Ddcn10_fpu.c119 .num_banks = 8,
/drivers/edac/
A Dqcom_edac.c297 for (i = 0; i < drv->num_banks; i++) { in llcc_ecc_irq_handler()
353 llcc_driv_data->num_banks, 1, in qcom_llcc_edac_probe()
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_plane.c185 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() local
191 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
195 tiling_info->gfx8.num_banks = num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
219 tiling_info->gfx9.num_banks = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
220 adev->gfx.config.gb_addr_config_fields.num_banks; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
256 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier()
457 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); in amdgpu_dm_plane_add_gfx9_modifiers()
/drivers/crypto/intel/qat/qat_c3xxxvf/
A Dadf_c3xxxvf_hw_data.c64 hw_data->num_banks = ADF_C3XXXIOV_ETR_MAX_BANKS; in adf_init_hw_data_c3xxxiov()
/drivers/crypto/intel/qat/qat_c62xvf/
A Dadf_c62xvf_hw_data.c64 hw_data->num_banks = ADF_C62XIOV_ETR_MAX_BANKS; in adf_init_hw_data_c62xiov()
/drivers/crypto/intel/qat/qat_dh895xccvf/
A Dadf_dh895xccvf_hw_data.c64 hw_data->num_banks = ADF_DH895XCCIOV_ETR_MAX_BANKS; in adf_init_hw_data_dh895xcciov()
/drivers/pinctrl/meson/
A Dpinctrl-meson.h119 unsigned int num_banks; member
/drivers/crypto/intel/qat/qat_6xxx/
A Dadf_6xxx_hw_data.c448 if (bank_number >= hw_data->num_banks) in ring_pair_reset()
626 for (i = 0; i < hw_data->num_banks; i++) { in adf_gen6_set_vc()
880 hw_data->num_banks = ADF_GEN6_ETR_MAX_BANKS; in adf_init_hw_data_6xxx()
/drivers/pinctrl/bcm/
A Dpinctrl-iproc-gpio.c113 unsigned num_banks; member
175 for (i = 0; i < chip->num_banks; i++) { in iproc_gpio_irq_handler()
860 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; in iproc_gpio_probe()
/drivers/gpu/drm/amd/display/dc/
A Ddc_hw_types.h363 unsigned int num_banks; member
425 unsigned int num_banks; member

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