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Searched refs:num_clk_values (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/
A Ddml2_mcg_dcn4.c50 if (soc_bb->clk_table.dcfclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
54 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
62 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_fine_grained()
67 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_fine_grained()
137 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_coarse_grained()
155 if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2) in build_min_clock_table()
158 if (soc_bb->clk_table.uclk.num_clk_values > DML_MCG_MAX_CLK_TABLE_SIZE) in build_min_clock_table()
161 if (soc_bb->clk_table.dcfclk.num_clk_values == 2) { in build_min_clock_table()
165 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clock_table()
169 if (soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.dcfclk.num_clk_values && in build_min_clock_table()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/
A Ddcn4_soc_bb.h88 .num_clk_values = 1,
92 .num_clk_values = 2,
96 .num_clk_values = 2,
100 .num_clk_values = 2,
104 .num_clk_values = 2,
108 .num_clk_values = 2,
112 .num_clk_values = 2,
116 .num_clk_values = 2,
120 .num_clk_values = 2,
124 .num_clk_values = 2,
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c111 dml_clk_table->dcfclk.num_clk_values = i; in override_dml_init_with_values_from_smu()
126 if (i < dml_clk_table->fclk.num_clk_values) { in override_dml_init_with_values_from_smu()
131 dml_clk_table->fclk.num_clk_values = i + 1; in override_dml_init_with_values_from_smu()
134 dml_clk_table->fclk.num_clk_values = i; in override_dml_init_with_values_from_smu()
149 if (i < dml_clk_table->uclk.num_clk_values) { in override_dml_init_with_values_from_smu()
154 dml_clk_table->uclk.num_clk_values = i + 1; in override_dml_init_with_values_from_smu()
157 dml_clk_table->uclk.num_clk_values = i; in override_dml_init_with_values_from_smu()
180 dml_clk_table->dispclk.num_clk_values = i; in override_dml_init_with_values_from_smu()
203 dml_clk_table->dppclk.num_clk_values = i; in override_dml_init_with_values_from_smu()
226 dml_clk_table->dtbclk.num_clk_values = i; in override_dml_init_with_values_from_smu()
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A Ddml21_wrapper.c153 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
155 …_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; in dml21_calculate_rq_and_dlg_params()
160 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
162 …lk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; in dml21_calculate_rq_and_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c263 if (clock_table->num_clk_values > 2) { in round_up_and_copy_to_next_dpm()
264 while (index < clock_table->num_clk_values && clock_table->clk_values_khz[index] < min_value) in round_up_and_copy_to_next_dpm()
267 if (index < clock_table->num_clk_values) { in round_up_and_copy_to_next_dpm()
271 } else if (clock_table->clk_values_khz[clock_table->num_clk_values - 1] >= min_value) { in round_up_and_copy_to_next_dpm()
327 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
341 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
371 if (state_table->dcfclk.num_clk_values == 2) { in map_min_clocks_to_dpm()
375 if (state_table->fclk.num_clk_values == 2) { in map_min_clocks_to_dpm()
379 if (state_table->fclk.num_clk_values == state_table->dcfclk.num_clk_values && in map_min_clocks_to_dpm()
380 state_table->fclk.num_clk_values == state_table->uclk.num_clk_values) { in map_min_clocks_to_dpm()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_soc_parameter_types.h109 unsigned char num_clk_values; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_utils.c538 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in dml2_core_utils_get_active_min_uclk_dpm_index()
A Ddml2_core_dcn4.c533 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in lookup_uclk_dpm_index_by_freq()
A Ddml2_core_dcn4_calcs.c7106 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in get_active_min_uclk_dpm_index()
11988 …e_lib->soc.clk_table.uclk.clk_values_khz[mode_lib->soc.clk_table.uclk.num_clk_values - 1] / 1000.0; in dml_core_mode_programming()

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