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Searched refs:num_dcfclk_levels (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c105 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
246 &num_entries_per_clk->num_dcfclk_levels); in dcn401_init_clocks()
248 if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz == in dcn401_init_clocks()
249 … clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz) in dcn401_init_clocks()
286 if (num_entries_per_clk->num_dcfclk_levels && in dcn401_init_clocks()
319 ((clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels && in dcn401_is_dc_mode_present()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_wrapper.h168 unsigned int num_dcfclk_levels; member
A Ddml2_translation_helper.c522 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++)… in dml2_init_soc_states()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h130 unsigned int num_dcfclk_levels; member
/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c869 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn321_update_bw_bounding_box_fpu()
870 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn321_update_bw_bounding_box_fpu()
891 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) { in dcn321_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c193 &num_entries_per_clk->num_dcfclk_levels); in dcn32_init_clocks()
231 if (num_entries_per_clk->num_dcfclk_levels && in dcn32_init_clocks()
/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c407 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn351_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c374 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn35_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c100 if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { in override_dml_init_with_values_from_smu()
101 dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; in override_dml_init_with_values_from_smu()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c3320 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn32_update_bw_bounding_box_fpu()
3321 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn32_update_bw_bounding_box_fpu()
3341 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c1021 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()

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