num_dcfclk_sta_targets (reference) in projects: drivers - OpenGrok search results

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Searched refs:num_dcfclk_sta_targets (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn302/
A D	dcn302_fpu.c	206 unsigned int num_dcfclk_sta_targets = 4; in dcn302_fpu_update_bw_bounding_box() local 242 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box() 244 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box() 245 num_dcfclk_sta_targets++; in dcn302_fpu_update_bw_bounding_box() 246 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box() 248 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn302_fpu_update_bw_bounding_box() 255 num_dcfclk_sta_targets = i + 1; in dcn302_fpu_update_bw_bounding_box() 269 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn302_fpu_update_bw_bounding_box() 282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box() 283 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn302_fpu_update_bw_bounding_box() [all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn303/
A D	dcn303_fpu.c	202 unsigned int num_dcfclk_sta_targets = 4; in dcn303_fpu_update_bw_bounding_box() local 238 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box() 239 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box() 240 num_dcfclk_sta_targets++; in dcn303_fpu_update_bw_bounding_box() 241 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box() 242 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn303_fpu_update_bw_bounding_box() 249 num_dcfclk_sta_targets = i + 1; in dcn303_fpu_update_bw_bounding_box() 263 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn303_fpu_update_bw_bounding_box() 287 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box() 288 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn303_fpu_update_bw_bounding_box() [all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A D	dcn321_fpu.c	718 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn321_update_bw_bounding_box_fpu() local 740 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu() 742 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu() 743 num_dcfclk_sta_targets++; in dcn321_update_bw_bounding_box_fpu() 744 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu() 746 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn321_update_bw_bounding_box_fpu() 753 num_dcfclk_sta_targets = i + 1; in dcn321_update_bw_bounding_box_fpu() 768 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn321_update_bw_bounding_box_fpu() 781 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu() 782 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn321_update_bw_bounding_box_fpu() [all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A D	dcn30_resource.c	2109 unsigned int num_dcfclk_sta_targets = 4; in dcn30_update_bw_bounding_box() local 2140 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box() 2142 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz; in dcn30_update_bw_bounding_box() 2143 num_dcfclk_sta_targets++; in dcn30_update_bw_bounding_box() 2144 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box() 2146 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn30_update_bw_bounding_box() 2153 num_dcfclk_sta_targets = i + 1; in dcn30_update_bw_bounding_box() 2170 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn30_update_bw_bounding_box() 2194 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box() 2195 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn30_update_bw_bounding_box() [all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A D	dcn32_fpu.c	3163 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn32_update_bw_bounding_box_fpu() local 3190 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu() 3192 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn32_update_bw_bounding_box_fpu() 3193 num_dcfclk_sta_targets++; in dcn32_update_bw_bounding_box_fpu() 3194 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu() 3196 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn32_update_bw_bounding_box_fpu() 3203 num_dcfclk_sta_targets = i + 1; in dcn32_update_bw_bounding_box_fpu() 3218 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn32_update_bw_bounding_box_fpu() 3231 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu() 3232 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn32_update_bw_bounding_box_fpu() [all …]

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