| /drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| A D | dce60_resource.c | 377 .num_ddc = 6,
385 .num_ddc = 6,
393 .num_ddc = 2,
822 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
1076 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1274 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1471 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| A D | dce80_resource.c | 379 .num_ddc = 6,
387 .num_ddc = 6,
395 .num_ddc = 2,
828 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
1086 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1286 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1483 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| A D | dce112_resource.c | 397 .num_ddc = 6,
405 .num_ddc = 5,
802 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1375 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| A D | dce100_resource.c | 379 .num_ddc = 6,
781 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
1125 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| A D | dce110_resource.c | 390 .num_ddc = 3,
399 .num_ddc = 3,
837 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1486 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 496 .num_ddc = 4,
506 .num_ddc = 4,
944 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1610 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| A D | dce120_resource.c | 503 .num_ddc = 6,
626 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1225 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | resource.h | 53 int num_ddc; member
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 128 .num_ddc = 5,
1036 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1455 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 126 .num_ddc = 2,
981 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
1388 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 579 .num_ddc = 5,
693 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
1620 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 648 .num_ddc = 4,
1085 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1678 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 571 .num_ddc = 2,
1238 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 818 .num_ddc = 5,
1411 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1982 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 836 .num_ddc = 5,
1472 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
2089 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_i2c_hw.c | 456 if (line < pool->res_cap->num_ddc) in acquire_i2c_hw_engine()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 663 .num_ddc = 6,
701 .num_ddc = 5,
1123 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
2641 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 824 .num_ddc = 5,
1415 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
2166 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 652 .num_ddc = 5,
1401 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1971 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 678 .num_ddc = 5,
1484 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn35_resource_destruct()
2124 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn35_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 823 .num_ddc = 5,
1415 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
2114 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 658 .num_ddc = 5,
1464 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn351_resource_destruct()
2095 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn351_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 659 .num_ddc = 5,
1465 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn36_resource_destruct()
2097 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn36_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 677 .num_ddc = 6,
1114 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
2558 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 647 .num_ddc = 4,
1423 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn401_resource_destruct()
2162 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn401_resource_construct()
|