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Searched refs:num_dispclk_levels (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c94 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
275 &num_entries_per_clk->num_dispclk_levels); in dcn401_init_clocks()
277 …if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz … in dcn401_init_clocks()
278 …clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mh… in dcn401_init_clocks()
288 num_entries_per_clk->num_dispclk_levels) in dcn401_init_clocks()
292 for (i = 0; i < num_entries_per_clk->num_dispclk_levels; i++) in dcn401_init_clocks()
321 (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels && in dcn401_is_dc_mode_present()
1511 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn401_get_max_clock_khz()
1521 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn401_get_max_clock_khz()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_wrapper.h173 unsigned int num_dispclk_levels; member
A Ddml2_translation_helper.c551 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++… in dml2_init_soc_states()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h135 unsigned int num_dispclk_levels; member
/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c884 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn321_update_bw_bounding_box_fpu()
885 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn321_update_bw_bounding_box_fpu()
921 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) { in dcn321_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c214 &num_entries_per_clk->num_dispclk_levels); in dcn32_init_clocks()
215 num_levels = num_entries_per_clk->num_dispclk_levels; in dcn32_init_clocks()
233 num_entries_per_clk->num_dispclk_levels) in dcn32_init_clocks()
/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c411 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn351_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c378 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn35_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c169 if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { in override_dml_init_with_values_from_smu()
170 dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; in override_dml_init_with_values_from_smu()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c3335 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn32_update_bw_bounding_box_fpu()
3336 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn32_update_bw_bounding_box_fpu()
3371 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c1022 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()

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