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Searched refs:num_dppclk_levels (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_wrapper.h174 unsigned int num_dppclk_levels; member
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h136 unsigned int num_dppclk_levels; member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c98 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
284 &num_entries_per_clk->num_dppclk_levels); in dcn401_init_clocks()
300 for (i = 0; i < num_entries_per_clk->num_dppclk_levels; i++) in dcn401_init_clocks()
1516 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels; in dcn401_get_max_clock_khz()
/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c887 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels = in dcn321_update_bw_bounding_box_fpu()
888 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels; in dcn321_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c224 &num_entries_per_clk->num_dppclk_levels); in dcn32_init_clocks()
225 num_levels = num_entries_per_clk->num_dppclk_levels; in dcn32_init_clocks()
/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c413 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels = in dcn351_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c380 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels = in dcn35_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c192 if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { in override_dml_init_with_values_from_smu()
193 dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; in override_dml_init_with_values_from_smu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c1023 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c3338 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels = in dcn32_update_bw_bounding_box_fpu()
3339 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels; in dcn32_update_bw_bounding_box_fpu()

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