| /drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| A D | dcn30_hwseq.h | 52 unsigned int num_dwb,
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| A D | dcn30_hwseq.c | 468 unsigned int num_dwb, in dcn30_mmhubbub_warmup() argument
476 for (i = 0; i < num_dwb; i++) { in dcn30_mmhubbub_warmup()
505 for (i = 0; i < num_dwb; i++) { in dcn30_mmhubbub_warmup()
591 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
621 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 127 .num_dwb = 1,
710 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
745 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1061 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 125 .num_dwb = 1,
672 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
707 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
1006 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 647 .num_dwb = 1,
1110 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1178 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1203 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | resource.h | 52 int num_dwb; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 817 .num_dwb = 1,
1436 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1509 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1534 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 835 .num_dwb = 1,
1497 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1573 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1598 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 823 .num_dwb = 1,
1440 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1516 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 651 .num_dwb = 1,
1426 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1487 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1516 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 677 .num_dwb = 1,
1509 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn35_resource_destruct()
1601 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1640 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 822 .num_dwb = 1,
1440 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1516 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 657 .num_dwb = 1,
1489 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn351_resource_destruct()
1581 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1620 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 658 .num_dwb = 1,
1490 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn36_resource_destruct()
1582 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1621 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 662 .num_dwb = 1,
700 .num_dwb = 1,
1148 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
2240 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2263 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 676 .num_dwb = 1,
1139 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1218 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1243 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 646 .num_dwb = 1,
1448 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn401_resource_destruct()
1509 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_dwbc_create()
1540 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 655 .num_dwb = 1,
1445 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1506 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1535 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 578 .num_dwb = 1,
718 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 330 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 569 .num_dwb = 0,
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 3207 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn20_fpga_init_hw()
|