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Searched refs:num_mec (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v9_4_3.c1026 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_alloc_ip_dump()
1062 adev->gfx.mec.num_mec = 2; in gfx_v9_4_3_sw_init()
1109 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_4_3_sw_init()
3157 for (j = 0; j < adev->gfx.mec.num_mec; j++) { in gfx_v9_4_3_set_priv_reg_fault_state()
3197 for (j = 0; j < adev->gfx.mec.num_mec; j++) { in gfx_v9_4_3_set_bad_op_fault_state()
4587 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_ip_print()
4593 adev->gfx.mec.num_mec, in gfx_v9_4_3_ip_print()
4600 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_4_3_ip_print()
4655 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_ip_dump()
4662 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_4_3_ip_dump()
A Dgfx_v12_0.c1367 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v12_0_alloc_ip_dump()
1408 adev->gfx.mec.num_mec = 1; in gfx_v12_0_sw_init()
1416 adev->gfx.mec.num_mec = 1; in gfx_v12_0_sw_init()
1525 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v12_0_sw_init()
3718 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { in gfx_v12_0_set_userq_eop_interrupts()
4904 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_0_set_priv_reg_fault_state()
4950 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_0_set_bad_op_fault_state()
5132 adev->gfx.mec.num_mec, in gfx_v12_ip_print()
5136 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_ip_print()
5197 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_ip_dump()
A Dgfx_v11_0.c1549 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v11_0_alloc_ip_dump()
1596 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1604 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1782 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_sw_init()
4844 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { in gfx_v11_0_set_userq_eop_interrupts()
4994 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_soft_reset()
6501 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6547 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_bad_op_fault_state()
7018 adev->gfx.mec.num_mec, in gfx_v11_ip_print()
7022 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_print()
[all …]
A Damdgpu_gfx.h110 u32 num_mec; member
A Dgfx_v7_0.c2745 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec in gfx_v7_0_mec_init()
3019 for (i = 0; i < adev->gfx.mec.num_mec; i++) in gfx_v7_0_cp_compute_resume()
4318 adev->gfx.mec.num_mec = 2; in gfx_v7_0_sw_init()
4325 adev->gfx.mec.num_mec = 1; in gfx_v7_0_sw_init()
4381 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v7_0_sw_init()
A Dgfx_v9_0.c2201 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_0_alloc_ip_dump()
2230 adev->gfx.mec.num_mec = 2; in gfx_v9_0_sw_init()
2233 adev->gfx.mec.num_mec = 1; in gfx_v9_0_sw_init()
2390 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_0_sw_init()
6041 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_0_set_priv_reg_fault_state()
6077 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_0_set_bad_op_fault_state()
7269 adev->gfx.mec.num_mec, in gfx_v9_ip_print()
7273 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_ip_print()
7315 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_ip_dump()
A Damdgpu_mes.c137 num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec; in amdgpu_mes_init()
A Dgfx_v10_0.c4728 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v10_0_alloc_ip_dump()
4771 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4786 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4794 adev->gfx.mec.num_mec = 1; in gfx_v10_0_sw_init()
4939 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v10_0_sw_init()
9254 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_0_set_priv_reg_fault_state()
9300 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_0_set_bad_op_fault_state()
9671 adev->gfx.mec.num_mec, in gfx_v10_ip_print()
9675 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_ip_print()
9741 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_ip_dump()
A Damdgpu_gfx.c165 return adev->gfx.mec.num_mec > 1; in amdgpu_gfx_is_compute_multipipe_capable()
274 queue_bit = adev->gfx.mec.num_mec in amdgpu_gfx_kiq_acquire()
A Dgfx_v8_0.c1902 adev->gfx.mec.num_mec = 2; in gfx_v8_0_sw_init()
1907 adev->gfx.mec.num_mec = 1; in gfx_v8_0_sw_init()
1988 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
/drivers/gpu/drm/radeon/
A Dcik.c4386 rdev->mec.num_mec = 2; in cik_mec_init()
4388 rdev->mec.num_mec = 1; in cik_mec_init()
4390 rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8; in cik_mec_init()
4394 rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2, in cik_mec_init()
4424 memset(hpd, 0, rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2); in cik_mec_init()
4532 for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); ++i) { in cik_cp_compute_resume()
A Dradeon.h826 u32 num_mec; member

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