| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 130 .num_mpc_3dlut = 2,
1085 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1264 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 in dcn302_resource_construct()
1425 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 128 .num_mpc_3dlut = 1,
1030 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1209 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 in dcn303_resource_construct()
1358 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 650 .num_mpc_3dlut = 2,
1133 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1474 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn301_resource_construct()
1648 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 679 .num_mpc_3dlut = 3,
1162 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1443 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1473 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
2345 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3 in dcn30_resource_construct()
2528 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | resource.h | 60 int num_mpc_3dlut; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 820 .num_mpc_3dlut = 2,
1459 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1794 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn316_resource_construct()
1952 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn316_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 838 .num_mpc_3dlut = 2,
1520 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1880 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn314_resource_construct()
2059 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn314_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 826 .num_mpc_3dlut = 2,
1463 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1950 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn31_resource_construct()
2136 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn31_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 654 .num_mpc_3dlut = 4,
1449 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn321_resource_destruct()
1769 …dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before … in dcn321_resource_construct()
1939 …n321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); in dcn321_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 680 .num_mpc_3dlut = 2,
1532 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn35_resource_destruct()
1890 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn35_resource_construct()
2094 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn35_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 825 .num_mpc_3dlut = 2,
1463 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1918 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn315_resource_construct()
2084 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn315_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 660 .num_mpc_3dlut = 2,
1512 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn351_resource_destruct()
1862 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn351_resource_construct()
2065 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn351_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 661 .num_mpc_3dlut = 2,
1513 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn36_resource_destruct()
1863 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn36_resource_construct()
2067 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); in dcn36_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 658 .num_mpc_3dlut = 4,
1468 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn32_resource_destruct()
1626 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
2265 …dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before … in dcn32_resource_construct()
2440 …dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); in dcn32_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 649 .num_mpc_3dlut = 4,
1471 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn401_resource_destruct()
1943 …dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before … in dcn401_resource_construct()
2130 …n401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); in dcn401_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 467 for (i = 0; i < caps->num_mpc_3dlut; i++) { in resource_construct()
|