| /drivers/soc/mediatek/ |
| A D | mtk-dvfsrc.c | 52 u32 num_opp; member
212 if (level < dvfsrc->curr_opps->num_opp) in dvfsrc_get_current_level_v2()
213 return dvfsrc->curr_opps->num_opp - level; in dvfsrc_get_current_level_v2()
468 .num_opp = ARRAY_SIZE(dvfsrc_opp_mt6893_lp4),
500 .num_opp = ARRAY_SIZE(dvfsrc_opp_mt8183_lp4),
504 .num_opp = ARRAY_SIZE(dvfsrc_opp_mt8183_lp3),
508 .num_opp = ARRAY_SIZE(dvfsrc_opp_mt8183_lp3),
538 .num_opp = ARRAY_SIZE(dvfsrc_opp_mt8195_lp4),
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 186 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
297 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 564 .num_opp = 2,
949 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
1229 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | resource.h | 47 int num_opp; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 123 .num_opp = 5,
1049 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1387 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 121 .num_opp = 2,
994 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1320 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 1654 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn32_init_blank()
1659 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn32_init_blank()
1669 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { in dcn32_init_blank()
1673 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn32_init_blank()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 657 .num_opp = 6,
695 .num_opp = 5,
1136 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1338 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
2659 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 809 .num_opp = 4,
1424 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1909 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 827 .num_opp = 4,
1485 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
2008 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 815 .num_opp = 4,
1428 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
2085 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 669 .num_opp = 4,
1497 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn35_resource_destruct()
2043 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn35_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 814 .num_opp = 4,
1428 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
2033 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 649 .num_opp = 4,
1477 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn351_resource_destruct()
2014 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn351_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 650 .num_opp = 4,
1478 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn36_resource_destruct()
2016 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn36_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 491 .num_opp = 4,
501 .num_opp = 3,
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 573 .num_opp = 4,
706 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 642 .num_opp = 4,
1098 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 671 .num_opp = 6,
1127 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
2486 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 644 .num_opp = 4,
1414 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 639 .num_opp = 4,
1436 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn401_resource_destruct()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_hw_sequencer.c | 1219 int opp_count = dc->res_pool->res_cap->num_opp; in hwss_wait_for_outstanding_hw_updates()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 648 .num_opp = 4,
1433 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 429 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
442 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| A D | dcn35_hwseq.c | 761 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn35_init_pipes()
|