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Searched refs:num_pipe_per_me (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v12_0.c1406 adev->gfx.me.num_pipe_per_me = 1; in gfx_v12_0_sw_init()
1414 adev->gfx.me.num_pipe_per_me = 1; in gfx_v12_0_sw_init()
1508 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v12_0_sw_init()
1881 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_0_enable_gui_idle_interrupt()
3703 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { in gfx_v12_0_set_userq_eop_interrupts()
4892 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_0_set_priv_reg_fault_state()
4938 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_0_set_bad_op_fault_state()
4983 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_0_set_priv_inst_fault_state()
5158 adev->gfx.me.num_pipe_per_me, in gfx_v12_ip_print()
5162 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_ip_print()
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A Dgfx_v11_0.c1594 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1602 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1765 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_sw_init()
2199 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_enable_gui_idle_interrupt()
4829 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { in gfx_v11_0_set_userq_eop_interrupts()
5006 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_soft_reset()
6489 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6535 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_bad_op_fault_state()
7049 adev->gfx.me.num_pipe_per_me, in gfx_v11_ip_print()
7053 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_print()
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A Damdgpu_gfx.c84 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()
146 return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1; in amdgpu_gfx_is_graphics_multipipe_capable()
244 int max_queues_per_me = adev->gfx.me.num_pipe_per_me * num_queue_per_pipe; in amdgpu_gfx_graphics_queue_acquire()
250 pipe = i % adev->gfx.me.num_pipe_per_me; in amdgpu_gfx_graphics_queue_acquire()
251 queue = (i / adev->gfx.me.num_pipe_per_me) % in amdgpu_gfx_graphics_queue_acquire()
A Damdgpu_gfx.h392 uint32_t num_pipe_per_me; member
A Damdgpu_mes.c111 num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; in amdgpu_mes_init()
A Dgfx_v10_0.c4769 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4784 adev->gfx.me.num_pipe_per_me = 2; in gfx_v10_0_sw_init()
4792 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4924 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v10_0_sw_init()
5428 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_enable_gui_idle_interrupt()
9242 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_set_priv_reg_fault_state()
9288 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_set_bad_op_fault_state()
9333 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_set_priv_inst_fault_state()
9702 adev->gfx.me.num_pipe_per_me, in gfx_v10_ip_print()
9706 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_ip_print()
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