Home
last modified time | relevance | path

Searched refs:num_pipes (Results 1 – 25 of 73) sorted by relevance

123

/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_rq_dlg_calc_32.c46 const unsigned int num_pipes, in dml32_rq_dlg_get_rq_reg() argument
141 num_pipes, pipe_idx); in dml32_rq_dlg_get_rq_reg()
210 const unsigned int num_pipes, in dml32_rq_dlg_get_dlg_reg() argument
307 for (k = 0; k < num_pipes; ++k) { in dml32_rq_dlg_get_dlg_reg()
312 for (i = 0; i < num_pipes; i++) { in dml32_rq_dlg_get_dlg_reg()
318 for (j = i; j < num_pipes; j++) { in dml32_rq_dlg_get_dlg_reg()
391 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
417 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
483 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
496 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_32.h47 const unsigned int num_pipes,
67 const unsigned int num_pipes,
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_rq_dlg_calc_31.c850 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
1059 for (k = 0; k < num_pipes; ++k) { in dml_rq_dlg_get_dlg_params()
1064 for (i = 0; i < num_pipes; i++) { in dml_rq_dlg_get_dlg_params()
1070 for (j = i; j < num_pipes; j++) { in dml_rq_dlg_get_dlg_params()
1548 const unsigned int num_pipes, in dml31_rq_dlg_get_dlg_reg() argument
1560 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1562 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1563 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1564 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1565 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_rq_dlg_calc_314.c935 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
1146 for (k = 0; k < num_pipes; ++k) { in dml_rq_dlg_get_dlg_params()
1151 for (i = 0; i < num_pipes; i++) { in dml_rq_dlg_get_dlg_params()
1157 for (j = i; j < num_pipes; j++) { in dml_rq_dlg_get_dlg_params()
1636 const unsigned int num_pipes, in dml314_rq_dlg_get_dlg_reg() argument
1648 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1650 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1651 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1652 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1653 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_wrapper.c95 int num_pipes; in dml21_calculate_rq_and_dlg_params() local
127 if (num_pipes <= 0) in dml21_calculate_rq_and_dlg_params()
131 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { in dml21_calculate_rq_and_dlg_params()
310 int num_pipes; in dml21_prepare_mcache_programming() local
336 mcache_config->num_pipes = pln_prog->num_dpps_required; in dml21_prepare_mcache_programming()
344 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || in dml21_prepare_mcache_programming()
349 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { in dml21_prepare_mcache_programming()
363 mcache_config->num_pipes = pln_prog->num_dpps_required; in dml21_prepare_mcache_programming()
366 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { in dml21_prepare_mcache_programming()
384 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || in dml21_prepare_mcache_programming()
[all …]
A Ddml21_utils.c100 int num_pipes = 0; in dml21_find_dc_pipes_for_plane() local
111 return num_pipes; in dml21_find_dc_pipes_for_plane()
118 …num_pipes = dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_main_plane, &context->res_ctx, dc… in dml21_find_dc_pipes_for_plane()
123 …num_pipes = dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, &context->res_… in dml21_find_dc_pipes_for_plane()
128 if (dc_phantom_stream && num_pipes > 0) { in dml21_find_dc_pipes_for_plane()
142 return num_pipes; in dml21_find_dc_pipes_for_plane()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_rq_dlg_calc_30.c887 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
1184 for (k = 0; k < num_pipes; ++k) { in dml_rq_dlg_get_dlg_params()
1189 for (i = 0; i < num_pipes; i++) { in dml_rq_dlg_get_dlg_params()
1195 for (j = i; j < num_pipes; j++) { in dml_rq_dlg_get_dlg_params()
1247 num_pipes, in dml_rq_dlg_get_dlg_params()
1251 num_pipes, in dml_rq_dlg_get_dlg_params()
1730 const unsigned int num_pipes, in dml30_rq_dlg_get_dlg_reg() argument
1745 num_pipes); in dml30_rq_dlg_get_dlg_reg()
1752 num_pipes); in dml30_rq_dlg_get_dlg_reg()
1755 num_pipes); in dml30_rq_dlg_get_dlg_reg()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_rq_dlg_calc_21.c824 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
976 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml_rq_dlg_get_dlg_params()
1058 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1142 num_pipes, in dml_rq_dlg_get_dlg_params()
1147 num_pipes, in dml_rq_dlg_get_dlg_params()
1642 const unsigned int num_pipes, in dml21_rq_dlg_get_dlg_reg() argument
1654 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml21_rq_dlg_get_dlg_reg()
1658 num_pipes); in dml21_rq_dlg_get_dlg_reg()
1666 num_pipes); in dml21_rq_dlg_get_dlg_reg()
1670 num_pipes); in dml21_rq_dlg_get_dlg_reg()
[all …]
/drivers/gpu/drm/tidss/
A Dtidss_kms.c121 u32 num_pipes = 0; in tidss_dispc_modeset_init() local
177 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
178 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
179 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
180 num_pipes++; in tidss_dispc_modeset_init()
184 crtc_mask = (1 << num_pipes) - 1; in tidss_dispc_modeset_init()
188 for (i = 0; i < num_pipes; ++i) { in tidss_dispc_modeset_init()
/drivers/gpu/drm/omapdrm/
A Domap_drv.c306 for (i = 0; i < priv->num_pipes; i++) { in omap_disconnect_pipelines()
317 priv->num_pipes = 0; in omap_disconnect_pipelines()
337 pipe = &priv->pipes[priv->num_pipes++]; in omap_connect_pipelines()
420 if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) { in omap_modeset_init()
427 plane_crtc_mask = (1 << priv->num_pipes) - 1; in omap_modeset_init()
430 enum drm_plane_type type = i < priv->num_pipes in omap_modeset_init()
449 for (i = 0; i < priv->num_pipes; i++) { in omap_modeset_init()
477 for (i = 0; i < priv->num_pipes; ++i) { in omap_modeset_init()
488 for (i = 0; i < priv->num_pipes; i++) { in omap_modeset_init()
512 priv->num_planes, priv->num_pipes); in omap_modeset_init()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_rq_dlg_calc_20.c48 const unsigned int num_pipes,
778 const unsigned int num_pipes, in dml20_rq_dlg_get_dlg_params() argument
930 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_params()
1093 num_pipes, in dml20_rq_dlg_get_dlg_params()
1097 num_pipes, in dml20_rq_dlg_get_dlg_params()
1533 const unsigned int num_pipes, in dml20_rq_dlg_get_dlg_reg() argument
1545 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_reg()
1548 num_pipes); in dml20_rq_dlg_get_dlg_reg()
1555 num_pipes); in dml20_rq_dlg_get_dlg_reg()
1558 num_pipes); in dml20_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_20v2.c48 const unsigned int num_pipes,
778 const unsigned int num_pipes, in dml20v2_rq_dlg_get_dlg_params() argument
930 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_params()
1094 num_pipes, in dml20v2_rq_dlg_get_dlg_params()
1098 num_pipes, in dml20v2_rq_dlg_get_dlg_params()
1534 const unsigned int num_pipes, in dml20v2_rq_dlg_get_dlg_reg() argument
1546 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
1549 num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
1556 num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
1559 num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_20.h65 const unsigned int num_pipes,
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_mes.c93 int i, r, num_pipes; in amdgpu_mes_init() local
112 if (num_pipes > AMDGPU_MES_MAX_GFX_PIPES) in amdgpu_mes_init()
114 num_pipes, AMDGPU_MES_MAX_GFX_PIPES); in amdgpu_mes_init()
117 if (i >= num_pipes) in amdgpu_mes_init()
138 if (num_pipes > AMDGPU_MES_MAX_COMPUTE_PIPES) in amdgpu_mes_init()
140 num_pipes, AMDGPU_MES_MAX_COMPUTE_PIPES); in amdgpu_mes_init()
143 if (i >= num_pipes) in amdgpu_mes_init()
148 num_pipes = adev->sdma.num_instances; in amdgpu_mes_init()
149 if (num_pipes > AMDGPU_MES_MAX_SDMA_PIPES) in amdgpu_mes_init()
151 num_pipes, AMDGPU_MES_MAX_SDMA_PIPES); in amdgpu_mes_init()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.c47 unsigned int num_pipes);
55 unsigned int num_pipes) in dml_get_voltage_level() argument
59 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
66 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
84 recalculate_params(mode_lib, pipes, num_pipes); \
210 unsigned int num_pipes) in get_total_immediate_flip_bytes() argument
219 unsigned int num_pipes) in get_total_immediate_flip_bw() argument
232 unsigned int num_pipes) in get_total_prefetch_bw() argument
246 unsigned int num_pipes) in get_total_surface_size_in_mall_bytes() argument
960 unsigned int num_pipes) in recalculate_params() argument
[all …]
A Ddisplay_mode_lib.h56 const unsigned int num_pipes,
74 const unsigned int num_pipes,
79 const unsigned int num_pipes,
A Ddisplay_mode_vba.h34 …struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
75 …de_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int wh…
151 unsigned int num_pipes);
155 unsigned int num_pipes);
159 unsigned int num_pipes);
163 unsigned int num_pipes);
168 unsigned int num_pipes);
172 unsigned int num_pipes,
/drivers/gpu/drm/radeon/
A Dr420.c94 unsigned num_pipes; in r420_pipes_init() local
105 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; in r420_pipes_init()
110 num_pipes = 1; in r420_pipes_init()
112 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
114 switch (num_pipes) { in r420_pipes_init()
117 num_pipes = 1; in r420_pipes_init()
132 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); in r420_pipes_init()
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.h92 int num_pipes, struct dc_crtc_timing_adjust adjust);
95 int num_pipes, const struct dc_static_screen_params *params);
98 int num_pipes, uint32_t v_total_min, uint32_t v_total_max);
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.h153 int num_pipes, struct dc_crtc_timing_adjust adjust);
155 int num_pipes,
158 int num_pipes, const struct dc_static_screen_params *params);
/drivers/gpu/drm/amd/display/dc/hwss/
A Dhw_sequencer.h260 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
279 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
282 int num_pipes,
461 …void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t …
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_wrapper.c64 unsigned int num_pipes = 0; in map_hw_resources() local
85 …dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.… in map_hw_resources()
86 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true; in map_hw_resources()
87 …dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.d… in map_hw_resources()
88 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true; in map_hw_resources()
89 num_pipes++; in map_hw_resources()
A Ddml2_mall_phantom.c189 unsigned int num_pipes = 0; in get_num_free_pipes() local
196 num_pipes++; in get_num_free_pipes()
202 free_pipes = ctx->config.dcn_pipe_count - num_pipes; in get_num_free_pipes()
239 unsigned int num_pipes = 0; in assign_subvp_pipe() local
259 num_pipes++; in assign_subvp_pipe()
264 if (num_pipes <= free_pipes) { in assign_subvp_pipe()
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c2044 uint8_t i, num_pipes; in dce110_set_displaymarks() local
2047 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { in dce110_set_displaymarks()
2061 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], in dce110_set_displaymarks()
2064 num_pipes++; in dce110_set_displaymarks()
2069 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], in dce110_set_displaymarks()
2072 num_pipes++; in dce110_set_displaymarks()
2132 for (i = 0; i < num_pipes; i++) { in set_drr()
2150 int num_pipes, in get_position() argument
2157 for (i = 0; i < num_pipes; i++) in get_position()
2176 if (num_pipes) { in set_static_screen_control()
[all …]
/drivers/staging/media/atomisp/pci/
A Dsh_css.c123 int num_pipes; member
7819 int num_pipes, in ia_css_stream_create() argument
7836 if (num_pipes == 0 || in ia_css_stream_create()
7922 curr_stream->num_pipes = num_pipes; in ia_css_stream_create()
7925 curr_stream->num_pipes = 0; in ia_css_stream_create()
7934 for (i = 0; i < num_pipes; i++) in ia_css_stream_create()
8030 if (num_pipes >= 2) { in ia_css_stream_create()
8178 my_css_save.stream_seeds[i].num_pipes = num_pipes; in ia_css_stream_create()
8297 stream->num_pipes = 0; in ia_css_stream_destroy()
8492 if (stream->num_pipes == 2) { in ia_css_stream_get_shading_correction_binary()
[all …]

Completed in 107 milliseconds

123