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Searched refs:num_queue_per_pipe (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_gfx.c53 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
54 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
63 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
66 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
85 * num_queue_per_pipe; in amdgpu_gfx_me_queue_to_bit()
86 bit += pipe * num_queue_per_pipe; in amdgpu_gfx_me_queue_to_bit()
208 adev->gfx.mec.num_queue_per_pipe, in amdgpu_gfx_compute_queue_acquire()
219 adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_compute_queue_acquire()
252 num_queue_per_pipe; in amdgpu_gfx_graphics_queue_acquire()
254 set_bit(pipe * num_queue_per_pipe + queue, in amdgpu_gfx_graphics_queue_acquire()
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A Damdgpu_amdkfd.c181 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
202 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
A Damdgpu_amdkfd_gfx_v9.c75 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in kgd_gfx_v9_get_queue_mask()
962 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
963 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
1043 adev->gfx.mec.num_queue_per_pipe; in kgd_gfx_v9_get_cu_occupancy()
A Damdgpu_gfx.h112 u32 num_queue_per_pipe; member
393 uint32_t num_queue_per_pipe; member
A Dgfx_v12_0.c1368 adev->gfx.mec.num_queue_per_pipe; in gfx_v12_0_alloc_ip_dump()
1381 adev->gfx.me.num_queue_per_pipe; in gfx_v12_0_alloc_ip_dump()
1407 adev->gfx.me.num_queue_per_pipe = 8; in gfx_v12_0_sw_init()
1410 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v12_0_sw_init()
1415 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v12_0_sw_init()
1418 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v12_0_sw_init()
1455 adev->gfx.mec.num_queue_per_pipe) / 2; in gfx_v12_0_sw_init()
1507 for (j = 0; j < num_queue_per_pipe; j++) { in gfx_v12_0_sw_init()
1526 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v12_0_sw_init()
5134 adev->gfx.mec.num_queue_per_pipe); in gfx_v12_ip_print()
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A Dgfx_v11_0.c1550 adev->gfx.mec.num_queue_per_pipe; in gfx_v11_0_alloc_ip_dump()
1563 adev->gfx.me.num_queue_per_pipe; in gfx_v11_0_alloc_ip_dump()
1595 adev->gfx.me.num_queue_per_pipe = 2; in gfx_v11_0_sw_init()
1598 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v11_0_sw_init()
1603 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1606 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v11_0_sw_init()
1764 for (j = 0; j < num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1783 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
5005 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
7020 adev->gfx.mec.num_queue_per_pipe); in gfx_v11_ip_print()
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A Dgfx_v9_4_3.c1027 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_4_3_alloc_ip_dump()
1064 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_4_3_sw_init()
1110 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_4_3_sw_init()
4588 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_4_3_ip_print()
4595 adev->gfx.mec.num_queue_per_pipe); in gfx_v9_4_3_ip_print()
4602 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_4_3_ip_print()
4656 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_4_3_ip_dump()
4664 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_4_3_ip_dump()
A Dgfx_v10_0.c4729 adev->gfx.mec.num_queue_per_pipe; in gfx_v10_0_alloc_ip_dump()
4742 adev->gfx.me.num_queue_per_pipe; in gfx_v10_0_alloc_ip_dump()
4770 adev->gfx.me.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4773 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4785 adev->gfx.me.num_queue_per_pipe = 2; in gfx_v10_0_sw_init()
4788 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v10_0_sw_init()
4793 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4796 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4923 for (j = 0; j < num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
9673 adev->gfx.mec.num_queue_per_pipe); in gfx_v10_ip_print()
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A Damdgpu_amdkfd_gfx_v10_3.c69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
A Damdgpu_amdkfd_gfx_v11.c67 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
A Damdgpu_amdkfd_gfx_v10.c69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
A Dgfx_v9_0.c2202 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_0_alloc_ip_dump()
2275 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_0_sw_init()
2391 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_0_sw_init()
7271 adev->gfx.mec.num_queue_per_pipe); in gfx_v9_ip_print()
7275 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_ip_print()
7317 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_ip_dump()
A Dgfx_v7_0.c4329 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v7_0_sw_init()
4382 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v7_0_sw_init()
A Dgfx_v8_0.c1912 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v8_0_sw_init()
1989 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
/drivers/gpu/drm/amd/include/
A Dkgd_kfd_interface.h114 uint32_t num_queue_per_pipe; member
/drivers/gpu/drm/amd/amdkfd/
A Dkfd_device_queue_manager.c87 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe; in is_pipe_enabled()
90 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i) in is_pipe_enabled()
105 return dqm->dev->kfd->shared_resources.num_queue_per_pipe; in get_queues_per_pipe()
1707 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) in set_sched_resources()
1859 num_hw_queue_slots = dqm->dev->kfd->shared_resources.num_queue_per_pipe * in start_cpsch()
2154 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) in detect_queue_hang()

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