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Searched refs:num_reader_wm_sets (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c494 ranges->num_reader_wm_sets = num_valid_sets; in build_watermark_ranges()
499 …ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK… in build_watermark_ranges()
500 …ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_… in build_watermark_ranges()
/drivers/gpu/drm/amd/display/dc/
A Ddm_pp_smu.h90 unsigned int num_reader_wm_sets; member
/drivers/gpu/drm/amd/display/dc/resource/dcn301/
A Ddcn301_resource.c1329 ranges.num_reader_wm_sets = 0; in set_wm_ranges()
1338 ranges.num_reader_wm_sets = 1; in set_wm_ranges()
1347 ranges.num_reader_wm_sets = i + 1; in set_wm_ranges()
1351 …ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UN… in set_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_5_ppt.c419 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in smu_v13_0_5_set_watermarks_table()
423 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in smu_v13_0_5_set_watermarks_table()
A Dsmu_v13_0_4_ppt.c673 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in smu_v13_0_4_set_watermarks_table()
677 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in smu_v13_0_4_set_watermarks_table()
A Dyellow_carp_ppt.c510 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in yellow_carp_set_watermarks_table()
514 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in yellow_carp_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c2571 ranges.num_reader_wm_sets = 0; in dcn20_resource_construct()
2580 ranges.num_reader_wm_sets = 1; in dcn20_resource_construct()
2590 ranges.num_reader_wm_sets = i + 1; in dcn20_resource_construct()
2594 …ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UN… in dcn20_resource_construct()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c1068 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in renoir_set_watermarks_table()
1073 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in renoir_set_watermarks_table()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_0_ppt.c492 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in smu_v14_0_0_set_watermarks_table()
496 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in smu_v14_0_0_set_watermarks_table()
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c474 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; in pp_rv_set_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c1601 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in vangogh_set_watermarks_table()
1605 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in vangogh_set_watermarks_table()
A Dsienna_cichlid_ppt.c1881 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in sienna_cichlid_set_watermarks_table()
1885 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in sienna_cichlid_set_watermarks_table()
A Dnavi10_ppt.c2179 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in navi10_set_watermarks_table()
2183 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in navi10_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c1390 ranges.num_reader_wm_sets = WM_SET_COUNT; in dcn_bw_notify_pplib_of_wm_ranges()

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