Searched refs:num_se (Results 1 – 14 of 14) sorted by relevance
| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | vega10_powertune.c | 887 uint32_t num_se = 0, count, data; in vega10_enable_cac_driving_se_didt_config() local
889 num_se = adev->gfx.config.max_shader_engines; in vega10_enable_cac_driving_se_didt_config()
894 for (count = 0; count < num_se; count++) { in vega10_enable_cac_driving_se_didt_config()
938 uint32_t num_se = 0, count, data; in vega10_enable_psm_gc_didt_config() local
940 num_se = adev->gfx.config.max_shader_engines; in vega10_enable_psm_gc_didt_config()
945 for (count = 0; count < num_se; count++) { in vega10_enable_psm_gc_didt_config()
999 uint32_t num_se = 0, count, data; in vega10_enable_se_edc_config() local
1001 num_se = adev->gfx.config.max_shader_engines; in vega10_enable_se_edc_config()
1006 for (count = 0; count < num_se; count++) { in vega10_enable_se_edc_config()
1046 uint32_t num_se = 0; in vega10_enable_psm_gc_edc_config() local
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| A D | smu7_powertune.c | 961 uint32_t num_se = 0; in smu7_enable_didt_config() local
966 num_se = adev->gfx.config.max_shader_engines; in smu7_enable_didt_config()
977 for (count = 0; count < num_se; count++) { in smu7_enable_didt_config()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | gfx_v6_0.c | 1381 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v6_0_write_harvested_raster_configs() local
1382 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); in gfx_v6_0_write_harvested_raster_configs()
1383 unsigned rb_per_se = num_rb / num_se; in gfx_v6_0_write_harvested_raster_configs()
1392 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); in gfx_v6_0_write_harvested_raster_configs()
1396 for (se = 0; se < num_se; se++) { in gfx_v6_0_write_harvested_raster_configs()
1402 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v6_0_write_harvested_raster_configs()
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| A D | gfx_v7_0.c | 1646 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v7_0_write_harvested_raster_configs() local
1647 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); in gfx_v7_0_write_harvested_raster_configs()
1648 unsigned rb_per_se = num_rb / num_se; in gfx_v7_0_write_harvested_raster_configs()
1657 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); in gfx_v7_0_write_harvested_raster_configs()
1661 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v7_0_write_harvested_raster_configs()
1674 for (se = 0; se < num_se; se++) { in gfx_v7_0_write_harvested_raster_configs()
1680 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v7_0_write_harvested_raster_configs()
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| A D | amdgpu_gfx.h | 221 uint8_t num_se; member
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| A D | gfx_v8_0.c | 3475 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v8_0_write_harvested_raster_configs() local
3476 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); in gfx_v8_0_write_harvested_raster_configs()
3477 unsigned rb_per_se = num_rb / num_se; in gfx_v8_0_write_harvested_raster_configs()
3486 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); in gfx_v8_0_write_harvested_raster_configs()
3490 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v8_0_write_harvested_raster_configs()
3503 for (se = 0; se < num_se; se++) { in gfx_v8_0_write_harvested_raster_configs()
3509 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v8_0_write_harvested_raster_configs()
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| A D | amdgpu_display.c | 848 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in convert_tiling_flags_to_modifier()
851 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in convert_tiling_flags_to_modifier()
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| A D | gfx_v9_4_3.c | 956 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_4_3_gpu_early_init()
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| A D | gfx_v12_0.c | 3560 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()
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| A D | gfx_v11_0.c | 4698 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()
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| A D | gfx_v9_0.c | 2139 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()
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| A D | gfx_v10_0.c | 4642 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v10_0_gpu_early_init()
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| /drivers/iio/adc/ |
| A D | stm32-adc.c | 2184 int num_se = nchans - num_diff; in stm32_adc_legacy_chan_init() local
2211 if (num_se > 0) { in stm32_adc_legacy_chan_init()
2212 ret = device_property_read_u32_array(dev, "st,adc-channels", chans, num_se); in stm32_adc_legacy_chan_init()
2218 for (c = 0; c < num_se; c++) { in stm32_adc_legacy_chan_init()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_plane.c | 224 adev->gfx.config.gb_addr_config_fields.num_se; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
455 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in amdgpu_dm_plane_add_gfx9_modifiers()
458 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in amdgpu_dm_plane_add_gfx9_modifiers()
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