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Searched refs:num_socclk_levels (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_wrapper.h171 unsigned int num_socclk_levels; member
A Ddml2_translation_helper.c540 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++)… in dml2_init_soc_states()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h133 unsigned int num_socclk_levels; member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c82 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
255 &num_entries_per_clk->num_socclk_levels); in dcn401_init_clocks()
257 if (num_entries_per_clk->num_socclk_levels && clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz == in dcn401_init_clocks()
258 … clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_socclk_levels - 1].socclk_mhz) in dcn401_init_clocks()
329 (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels && in dcn401_is_dc_mode_present()
/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c878 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn321_update_bw_bounding_box_fpu()
879 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; in dcn321_update_bw_bounding_box_fpu()
909 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) { in dcn321_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c415 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn351_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c382 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn35_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c238 if (dc_clk_table->num_entries_per_clk.num_socclk_levels) { in override_dml_init_with_values_from_smu()
239 dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; in override_dml_init_with_values_from_smu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c199 &num_entries_per_clk->num_socclk_levels); in dcn32_init_clocks()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c3329 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn32_update_bw_bounding_box_fpu()
3330 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; in dcn32_update_bw_bounding_box_fpu()
3359 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c1026 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()

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