| /drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| A D | dce60_resource.c | 373 .num_timing_generator = 6,
381 .num_timing_generator = 4,
389 .num_timing_generator = 2,
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
961 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1158 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1159 pool->base.timing_generator_count = res_cap_61.num_timing_generator; in dce61_construct()
1356 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1357 pool->base.timing_generator_count = res_cap_64.num_timing_generator; in dce64_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| A D | dce80_resource.c | 375 .num_timing_generator = 6,
383 .num_timing_generator = 4,
391 .num_timing_generator = 2,
966 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
967 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1168 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1169 pool->base.timing_generator_count = res_cap_81.num_timing_generator; in dce81_construct()
1368 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1369 pool->base.timing_generator_count = res_cap_83.num_timing_generator; in dce83_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 641 .num_timing_generator = 4,
1103 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1149 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1302 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
1432 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1433 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1635 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 122 .num_timing_generator = 5,
1054 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1217 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1218 pool->mpcc_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1396 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_construct()
1415 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 120 .num_timing_generator = 2,
999 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1159 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1160 pool->mpcc_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1329 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_construct()
1348 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 808 .num_timing_generator = 4,
1429 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1475 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1747 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
1748 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
1919 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_construct()
1939 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 826 .num_timing_generator = 4,
1490 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1536 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1830 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn314_resource_construct()
1831 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn314_resource_construct()
2018 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_construct()
2046 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 814 .num_timing_generator = 4,
1433 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1479 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1901 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
1902 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2095 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_construct()
2123 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 643 .num_timing_generator = 4,
1419 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1674 num_pipes = pool->base.res_cap->num_timing_generator; in dcn321_resource_construct()
1677 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) in dcn321_resource_construct()
1876 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_construct()
1939 …pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_… in dcn321_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 668 .num_timing_generator = 4,
1502 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1548 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1836 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn35_resource_construct()
1837 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn35_resource_construct()
2053 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_construct()
2081 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 813 .num_timing_generator = 4,
1433 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1479 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1871 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
1872 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
2043 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_construct()
2071 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 648 .num_timing_generator = 4,
1482 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1528 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1808 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn351_resource_construct()
1809 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn351_resource_construct()
2024 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_construct()
2052 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 649 .num_timing_generator = 4,
1483 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1529 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1809 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn36_resource_construct()
1810 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn36_resource_construct()
2026 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_construct()
2054 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 563 .num_timing_generator = 2,
954 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1194 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1254 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| A D | dce112_resource.c | 393 .num_timing_generator = 6,
401 .num_timing_generator = 5,
1240 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1241 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 603 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
675 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
742 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| A D | dce100_resource.c | 375 .num_timing_generator = 6,
1068 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1069 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 670 .num_timing_generator = 6,
1132 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1509 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
2299 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn30_resource_construct()
2300 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn30_resource_construct()
2496 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_construct()
2516 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 638 .num_timing_generator = 4,
1441 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1487 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1852 num_pipes = pool->base.res_cap->num_timing_generator; in dcn401_resource_construct()
1855 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) in dcn401_resource_construct()
2067 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_construct()
2130 …pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_… in dcn401_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| A D | dce110_resource.c | 385 .num_timing_generator = 3,
394 .num_timing_generator = 2,
1368 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1370 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 647 .num_timing_generator = 4,
1438 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1484 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
2166 num_pipes = pool->base.res_cap->num_timing_generator; in dcn32_resource_construct()
2169 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) in dcn32_resource_construct()
2372 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_construct()
2440 …pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_ca… in dcn32_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| A D | dce120_resource.c | 499 .num_timing_generator = 6,
1079 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1080 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | resource.h | 46 int num_timing_generator; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 490 .num_timing_generator = 4,
500 .num_timing_generator = 3,
1344 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 572 .num_timing_generator = 4,
711 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
1407 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
|