| /drivers/net/ethernet/mellanox/mlx5/core/lib/ |
| A D | crypto.c | 190 u32 obj_id, u32 obj_offset) in mlx5_crypto_modify_dek_key() argument
204 MLX5_SET(general_obj_query_param, param, obj_offset, obj_offset); in mlx5_crypto_modify_dek_key()
370 mlx5_crypto_dek_pool_pop(struct mlx5_crypto_dek_pool *pool, u32 *obj_offset) in mlx5_crypto_dek_pool_pop() argument
401 *obj_offset = pos; in mlx5_crypto_dek_pool_pop()
430 int obj_offset; in mlx5_crypto_dek_free_locked() local
434 obj_offset = dek->obj_id - bulk->base_obj_id; in mlx5_crypto_dek_free_locked()
435 old_val = test_and_clear_bit(obj_offset, bulk->in_use); in mlx5_crypto_dek_free_locked()
611 int obj_offset; in mlx5_crypto_dek_create() local
624 bulk = mlx5_crypto_dek_pool_pop(dek_pool, &obj_offset); in mlx5_crypto_dek_create()
631 dek->obj_id = bulk->base_obj_id + obj_offset; in mlx5_crypto_dek_create()
[all …]
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| /drivers/gpu/drm/i915/gem/ |
| A D | i915_gem_mman.c | 256 unsigned long obj_offset; in vm_fault_cpu() local
278 obj_offset = area->vm_pgoff - drm_vma_node_start(&mmo->vma_node); in vm_fault_cpu()
282 obj->mm.pages->sgl, obj_offset, iomap); in vm_fault_cpu()
298 unsigned long obj_offset, in set_address_limits() argument
321 start -= obj_offset; in set_address_limits()
334 *pfn += obj_offset - vma->gtt_view.partial.offset; in set_address_limits()
349 unsigned long obj_offset; in vm_fault_gtt() local
358 obj_offset = area->vm_pgoff - drm_vma_node_start(&mmo->vma_node); in vm_fault_gtt()
360 page_offset += obj_offset; in vm_fault_gtt()
458 set_address_limits(area, vma, obj_offset, ggtt->gmadr.start, in vm_fault_gtt()
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/sws/ |
| A D | dr_arg.c | 82 arg_obj->obj_offset = i * (1 << pool->log_chunk_size); in dr_arg_pool_alloc_objs()
162 if (!arg_obj->obj_offset) /* the first in range */ in dr_arg_pool_destroy()
187 return (arg_obj->obj_id + arg_obj->obj_offset); in mlx5dr_arg_get_obj_id()
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| A D | dr_types.h | 1027 u32 obj_offset; member
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| /drivers/gpu/drm/msm/ |
| A D | msm_gem_vma.c | 143 uint64_t obj_offset; member
943 job->ops[i].obj_offset = op->obj_offset; in lookup_op()
954 if (invalid_alignment(op->obj_offset)) in lookup_op()
955 ret = UERR(EINVAL, dev, "invalid bo_offset: %016llx\n", op->obj_offset); in lookup_op()
1171 op->obj_offset); in vm_bind_job_lock_objects()
1177 op->obj, op->obj_offset); in vm_bind_job_lock_objects()
1287 op->range, op->obj, op->obj_offset); in vm_bind_job_prepare()
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| /drivers/gpu/drm/xe/ |
| A D | xe_vm.c | 3344 u64 obj_offset = (*bind_ops)[i].obj_offset; in vm_bind_ioctl_check_args() local
3380 XE_IOCTL_DBG(xe, obj_offset && (is_null || in vm_bind_ioctl_check_args()
3409 if (XE_IOCTL_DBG(xe, obj_offset & ~PAGE_MASK) || in vm_bind_ioctl_check_args()
3464 u64 addr, u64 range, u64 obj_offset, in xe_vm_bind_ioctl_validate_bo() argument
3470 XE_IOCTL_DBG(xe, obj_offset > in xe_vm_bind_ioctl_validate_bo()
3485 if (XE_IOCTL_DBG(xe, obj_offset & in xe_vm_bind_ioctl_validate_bo()
3603 u64 obj_offset = bind_ops[i].obj_offset; in xe_vm_bind_ioctl() local
3619 obj_offset, pat_index, op, in xe_vm_bind_ioctl()
3664 u64 obj_offset = bind_ops[i].obj_offset; in xe_vm_bind_ioctl() local
3668 ops[i] = vm_bind_ioctl_ops_create(vm, &vops, bos[i], obj_offset, in xe_vm_bind_ioctl()
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| /drivers/gpu/drm/i915/ |
| A D | i915_vma.c | 1139 pgoff_t obj_offset, in remap_contiguous_pages() argument
1146 iter = i915_gem_object_get_sg_dma(obj, obj_offset, &offset); in remap_contiguous_pages()
1172 pgoff_t obj_offset, unsigned int alignment_pad, in remap_linear_color_plane_pages() argument
1183 sg = remap_contiguous_pages(obj, obj_offset, size, st, sg); in remap_linear_color_plane_pages()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_fb.c | 1487 u32 obj_offset, u32 gtt_offset, int x, int y, in calc_plane_remap_info() argument
1499 assign_bfld_chk_ovf(display, remap_info->offset, obj_offset); in calc_plane_remap_info()
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/ |
| A D | cmd.c | 596 op_param.query.obj_offset, stc_attr->stc_offset); in mlx5hws_cmd_stc_modify()
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