Home
last modified time | relevance | path

Searched refs:octeon_read_csr (Results 1 – 7 of 7) sorted by relevance

/drivers/net/ethernet/cavium/liquidio/
A Dcn66xx_device.c334 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE); in lio_cn6xxx_enable_io_queues()
338 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_enable_io_queues()
342 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_enable_io_queues()
356 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_disable_io_queues()
362 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_IQ); in lio_cn6xxx_disable_io_queues()
377 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_disable_io_queues()
384 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_OQ); in lio_cn6xxx_disable_io_queues()
402 d32 = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT); in lio_cn6xxx_disable_io_queues()
406 d32 = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT); in lio_cn6xxx_disable_io_queues()
544 value = octeon_read_csr(oct, reg); in lio_cn6xxx_process_droq_intr_regs()
[all …]
A Dlio_ethtool.c2922 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2925 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2929 reg, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2932 reg, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2940 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2943 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2950 octeon_read_csr(oct, CN6XXX_DMA_CNT(0))); in cn6xxx_read_csr_reg()
2957 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2961 octeon_read_csr(oct, CN6XXX_DMA_CNT(1))); in cn6xxx_read_csr_reg()
2965 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
[all …]
A Dcn23xx_pf_device.c325 reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no)); in cn23xx_pf_setup_global_output_regs()
486 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
494 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
686 reg_val = octeon_read_csr( in cn23xx_enable_io_queues()
764 WRITE_ONCE(d32, octeon_read_csr( in cn23xx_disable_io_queues()
979 oct->pcie_port = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff; in cn23xx_get_pcie_qlmport()
1010 mac = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff; in cn23xx_get_pf_num()
A Dcn23xx_vf_device.c161 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKTS_SENT(q_no)); in cn23xx_vf_setup_global_output_regs()
166 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); in cn23xx_vf_setup_global_output_regs()
346 reg_val = octeon_read_csr( in cn23xx_enable_vf_io_queues()
A Docteon_droq.c835 value = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB); in octeon_enable_irq()
838 value = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB); in octeon_enable_irq()
A Docteon_device.h739 #define octeon_read_csr(oct_dev, reg_off) \ macro
A Docteon_device.c1012 reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in octeon_set_droq_pkt_op()

Completed in 21 milliseconds