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/drivers/net/ethernet/marvell/octeontx2/af/
A Dmcs_reg.h21 offset; })
31 offset; })
39 offset; })
48 offset; })
56 offset; })
65 offset; })
73 offset; })
81 offset; })
91 offset; })
108 offset; })
[all …]
/drivers/net/ethernet/microchip/vcap/
A Dvcap_model_kunit.c20 .offset = 0,
25 .offset = 2,
30 .offset = 3,
35 .offset = 10,
40 .offset = 13,
45 .offset = 16,
50 .offset = 19,
55 .offset = 20,
60 .offset = 32,
65 .offset = 35,
[all …]
/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_vcap_ag_api.c20 .offset = 0,
25 .offset = 1,
30 .offset = 2,
35 .offset = 4,
40 .offset = 16,
45 .offset = 18,
50 .offset = 83,
55 .offset = 84,
60 .offset = 85,
65 .offset = 88,
[all …]
/drivers/net/ethernet/microchip/sparx5/lan969x/
A Dlan969x_vcap_ag_api.c19 .offset = 0,
24 .offset = 1,
29 .offset = 2,
34 .offset = 4,
39 .offset = 14,
44 .offset = 16,
49 .offset = 81,
54 .offset = 82,
59 .offset = 83,
64 .offset = 86,
[all …]
/drivers/net/ethernet/microchip/lan966x/
A Dlan966x_vcap_ag_api.c12 .offset = 0,
17 .offset = 1,
22 .offset = 3,
27 .offset = 12,
32 .offset = 13,
37 .offset = 14,
42 .offset = 15,
47 .offset = 16,
52 .offset = 17,
57 .offset = 18,
[all …]
A Dlan966x_ethtool.c12 { .name = "rx_octets", .offset = 0x00, },
13 { .name = "rx_unicast", .offset = 0x01, },
16 { .name = "rx_short", .offset = 0x04 },
17 { .name = "rx_frag", .offset = 0x05 },
18 { .name = "rx_jabber", .offset = 0x06 },
19 { .name = "rx_crc", .offset = 0x07 },
21 { .name = "rx_sz_64", .offset = 0x09 },
28 { .name = "rx_pause", .offset = 0x10 },
30 { .name = "rx_long", .offset = 0x12 },
112 { .name = "tx_ct", .offset = 0xa0 },
[all …]
/drivers/crypto/cavium/nitrox/
A Dnitrox_hal.c44 u64 offset; in nitrox_config_emu_unit() local
70 u64 offset; in reset_pkt_input_ring() local
98 u64 offset; in enable_pkt_input_ring() local
128 u64 offset; in nitrox_config_pkt_input_rings() local
166 u64 offset; in reset_pkt_solicit_port() local
195 u64 offset; in enable_pkt_solicit_port() local
221 u64 offset; in config_pkt_solicit_port() local
315 u64 offset; in reset_aqm_ring() local
343 u64 offset; in enable_aqm_ring() local
443 u64 offset; in nitrox_config_rand_unit() local
[all …]
/drivers/gpio/
A Dgpio-eic-sprd.c156 tmp |= BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update()
243 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_mask() local
340 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
342 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
345 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
347 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
372 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
374 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
377 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
379 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
[all …]
A Dgpio-aspeed.c503 int *offset) in irqd_to_aspeed_gpio_data() argument
523 int rc, offset; in aspeed_gpio_irq_ack() local
543 int rc, offset; in aspeed_gpio_irq_set_mask() local
585 int rc, offset; in aspeed_gpio_set_type() local
661 unsigned int offset; in aspeed_init_irq_valid_mask() local
738 offset, gpio->offset_timer[offset])) in register_allocated_timer()
753 unsigned int offset) in unregister_allocated_timer() argument
772 unsigned int offset) in timer_allocation_registered() argument
955 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_grab_gpio()
998 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_release_gpio()
[all …]
A Dgpio-cs5535.c86 if (offset < 16) in __cs5535_gpio_set()
108 if (offset < 16) in __cs5535_gpio_clear()
134 if (offset < 16) in cs5535_gpio_isset()
140 offset -= 16; in cs5535_gpio_isset()
172 if (offset >= 24) in cs5535_gpio_setup_event()
173 offset = GPIO_MAP_W; in cs5535_gpio_setup_event()
174 else if (offset >= 16) in cs5535_gpio_setup_event()
175 offset = GPIO_MAP_Z; in cs5535_gpio_setup_event()
176 else if (offset >= 8) in cs5535_gpio_setup_event()
177 offset = GPIO_MAP_Y; in cs5535_gpio_setup_event()
[all …]
A Dgpio-sprd.c53 offset / SPRD_GPIO_BANK_NR); in sprd_gpio_update()
61 tmp |= BIT(SPRD_GPIO_BIT(offset)); in sprd_gpio_update()
63 tmp &= ~BIT(SPRD_GPIO_BIT(offset)); in sprd_gpio_update()
73 offset / SPRD_GPIO_BANK_NR); in sprd_gpio_read()
90 unsigned int offset) in sprd_gpio_direction_input() argument
122 u32 offset = irqd_to_hwirq(data); in sprd_gpio_irq_mask() local
125 gpiochip_disable_irq(chip, offset); in sprd_gpio_irq_mask()
131 u32 offset = irqd_to_hwirq(data); in sprd_gpio_irq_ack() local
139 u32 offset = irqd_to_hwirq(data); in sprd_gpio_irq_unmask() local
142 gpiochip_enable_irq(chip, offset); in sprd_gpio_irq_unmask()
[all …]
/drivers/power/supply/
A Dmax1720x_battery.c154 { .name = "nXTable0", .offset = 0, .bytes = 2, },
155 { .name = "nXTable1", .offset = 2, .bytes = 2, },
156 { .name = "nXTable2", .offset = 4, .bytes = 2, },
157 { .name = "nXTable3", .offset = 6, .bytes = 2, },
158 { .name = "nXTable4", .offset = 8, .bytes = 2, },
159 { .name = "nXTable5", .offset = 10, .bytes = 2, },
160 { .name = "nXTable6", .offset = 12, .bytes = 2, },
161 { .name = "nXTable7", .offset = 14, .bytes = 2, },
162 { .name = "nXTable8", .offset = 16, .bytes = 2, },
163 { .name = "nXTable9", .offset = 18, .bytes = 2, },
[all …]
/drivers/net/wireless/ath/ath10k/
A Dqmi_wlfw_v01.c108 offset),
164 .offset = offsetof(struct wlfw_mem_cfg_s_v01,
165 offset),
173 .offset = offsetof(struct wlfw_mem_cfg_s_v01,
182 .offset = offsetof(struct wlfw_mem_cfg_s_v01,
195 .offset = offsetof(struct wlfw_mem_seg_s_v01,
204 .offset = offsetof(struct wlfw_mem_seg_s_v01,
213 .offset = offsetof(struct wlfw_mem_seg_s_v01,
222 .offset = offsetof(struct wlfw_mem_seg_s_v01,
1564 offset),
[all …]
/drivers/md/dm-vdo/
A Dencodings.c210 *offset += sizeof(packed); in encode_version_number()
218 *offset += sizeof(packed); in vdo_encode_header()
285 *offset += sizeof(u32); in decode_volume_geometry()
303 size_t offset = 0; in vdo_parse_geometry_block() local
380 initial_offset = *offset; in decode_block_map_state_2_0()
792 partition->offset = offset; in allocate_partition()
869 .start = offset, in vdo_initialize_layout()
871 .first_free = offset, in vdo_initialize_layout()
985 encode_u64_le(buffer, offset, partition->offset); in encode_layout()
1410 size_t offset = 0; in vdo_encode_super_block() local
[all …]
A Dnumeric.h21 *offset += sizeof(s64); in decode_s64_le()
26 put_unaligned_le64(to_encode, data + *offset); in encode_s64_le()
27 *offset += sizeof(s64); in encode_s64_le()
33 *offset += sizeof(u64); in decode_u64_le()
39 *offset += sizeof(u64); in encode_u64_le()
45 *offset += sizeof(s32); in decode_s32_le()
51 *offset += sizeof(s32); in encode_s32_le()
57 *offset += sizeof(u32); in decode_u32_le()
63 *offset += sizeof(u32); in encode_u32_le()
69 *offset += sizeof(u16); in decode_u16_le()
[all …]
/drivers/net/dsa/sja1105/
A Dsja1105_ethtool.c83 int offset; member
94 .offset = 0,
101 .offset = 0x0,
108 .offset = 0x0,
115 .offset = 0x0,
123 .offset = 0x1,
130 .offset = 0x1,
137 .offset = 0x1,
144 .offset = 0x1,
151 .offset = 0x1,
[all …]
/drivers/thunderbolt/
A Dcap.c21 u32 value, offset; in tb_port_enable_tmu() local
29 offset = 0x26; in tb_port_enable_tmu()
31 offset = 0x2a; in tb_port_enable_tmu()
77 if (!offset) in tb_port_next_cap()
89 int offset = 0; in __tb_port_find_cap() local
95 offset = tb_port_next_cap(port, offset); in __tb_port_find_cap()
96 if (offset < 0) in __tb_port_find_cap()
97 return offset; in __tb_port_find_cap()
150 if (!offset) in tb_switch_next_cap()
196 offset = tb_switch_next_cap(sw, offset); in tb_switch_find_cap()
[all …]
/drivers/misc/ocxl/
A Dmmio.c10 if (offset > afu->config.global_mmio_size - 4) in ocxl_global_mmio_read32()
24 *val = readl((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read32()
35 if (offset > afu->config.global_mmio_size - 8) in ocxl_global_mmio_read64()
49 *val = readq((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read64()
60 if (offset > afu->config.global_mmio_size - 4) in ocxl_global_mmio_write32()
74 writel(val, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_write32()
86 if (offset > afu->config.global_mmio_size - 8) in ocxl_global_mmio_write64()
114 if (offset > afu->config.global_mmio_size - 4) in ocxl_global_mmio_set32()
145 if (offset > afu->config.global_mmio_size - 8) in ocxl_global_mmio_set64()
176 if (offset > afu->config.global_mmio_size - 4) in ocxl_global_mmio_clear32()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
A Dinit.c665 init->offset += 2; in init_repeat()
727 init->offset += 1; in init_end_repeat()
731 init->offset = 0; in init_end_repeat()
770 init->offset += 1; in init_not()
785 init->offset += 2; in init_io_flag_condition()
806 init->offset += 3; in init_generic_condition()
1073 init->offset++; in init_zm_i2c()
1373 u16 offset = nvbios_rd16(bios, init->offset + 1); in init_jump() local
1378 init->offset = offset; in init_jump()
2203 for (i = init->offset; i < init->offset + count; i++) in init_gpio_ne()
[all …]
/drivers/staging/media/atomisp/pci/
A Dia_css_isp_configs.c18 unsigned int offset = 0; in ia_css_configure_iterator() local
30 offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; in ia_css_configure_iterator()
53 offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; in ia_css_configure_copy_output()
78 offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; in ia_css_configure_crop()
101 offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset; in ia_css_configure_fpn()
123 offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset; in ia_css_configure_dvs()
145 offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset; in ia_css_configure_qplane()
237 offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset; in ia_css_configure_raw()
260 offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset; in ia_css_configure_tnr()
283 offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset; in ia_css_configure_ref()
[all …]
/drivers/net/ipa/
A Dipa_qmi_msg.c21 .offset = offsetof(struct ipa_indication_register_req,
31 .offset = offsetof(struct ipa_indication_register_req,
41 .offset = offsetof(struct ipa_indication_register_req,
51 .offset = offsetof(struct ipa_indication_register_req,
181 .offset = offsetof(struct ipa_init_complete_ind,
197 .offset = offsetof(struct ipa_mem_bounds, start),
204 .offset = offsetof(struct ipa_mem_bounds, end),
218 .offset = offsetof(struct ipa_mem_array, start),
225 .offset = offsetof(struct ipa_mem_array, count),
239 .offset = offsetof(struct ipa_mem_range, start),
[all …]
/drivers/pinctrl/
A Dpinctrl-da9062.c26 #define DA9062_TYPE(offset) (4 * (offset % 2)) argument
27 #define DA9062_PIN_SHIFT(offset) (4 * (offset % 2)) argument
41 unsigned int offset) in da9062_pctl_get_pin_mode() argument
50 val >>= DA9062_PIN_SHIFT(offset); in da9062_pctl_get_pin_mode()
65 mode <<= DA9062_PIN_SHIFT(offset); in da9062_pctl_set_pin_mode()
102 return !!(val & BIT(offset)); in da9062_gpio_get()
112 value << offset); in da9062_gpio_set()
138 unsigned int offset) in da9062_gpio_direction_input() argument
196 BIT(offset), 0); in da9062_gpio_set_config()
204 BIT(offset), BIT(offset)); in da9062_gpio_set_config()
[all …]
/drivers/gpu/drm/i915/display/
A Ddvo_ns2501.c195 u8 offset; member
301 [0] = { .offset = 0x0a, .value = 0x81, },
303 [1] = { .offset = 0x12, .value = 0x02, },
304 [2] = { .offset = 0x18, .value = 0x07, },
305 [3] = { .offset = 0x19, .value = 0x00, },
308 [5] = { .offset = 0x1e, .value = 0x02, },
309 [6] = { .offset = 0x1f, .value = 0x40, },
310 [7] = { .offset = 0x20, .value = 0x00, },
311 [8] = { .offset = 0x21, .value = 0x00, },
312 [9] = { .offset = 0x22, .value = 0x00, },
[all …]
/drivers/hwtracing/coresight/
A Dcoresight-etm4x-cfg.c15 if (offset == cval) { \
53 if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) || in etm4_cfg_map_reg_offset()
54 ((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) || in etm4_cfg_map_reg_offset()
55 ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) { in etm4_cfg_map_reg_offset()
78 idx = (offset & GENMASK(3, 0)) / 4; in etm4_cfg_map_reg_offset()
83 } else if ((offset >= TRCSSCCRn(0)) && (offset <= TRCSSPCICRn(7))) { in etm4_cfg_map_reg_offset()
85 idx = (offset & GENMASK(4, 0)) / 4; in etm4_cfg_map_reg_offset()
92 } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) { in etm4_cfg_map_reg_offset()
94 idx = (offset & GENMASK(5, 0)) / 8; in etm4_cfg_map_reg_offset()
153 u32 offset; in etm4_cfg_load_feature() local
[all …]
/drivers/net/wireless/ath/ath6kl/
A Dbmi.c120 u32 offset; in ath6kl_bmi_read() local
145 offset = 0; in ath6kl_bmi_read()
176 u32 offset; in ath6kl_bmi_write() local
243 u32 offset; in ath6kl_bmi_execute() local
261 offset = 0; in ath6kl_bmi_execute()
290 u32 offset; in ath6kl_bmi_set_app_start() local
307 offset = 0; in ath6kl_bmi_set_app_start()
326 u32 offset; in ath6kl_bmi_reg_read() local
343 offset = 0; in ath6kl_bmi_reg_read()
369 u32 offset; in ath6kl_bmi_reg_write() local
[all …]

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