| /drivers/gpu/drm/xe/instructions/ |
| A D | xe_alu_commands.h | 58 #define CS_ALU_INSTR(opcode, op1, op2) (REG_FIELD_PREP(GENMASK(31, 20), (opcode)) | \ argument
60 REG_FIELD_PREP(GENMASK(9, 0), (op2)))
62 #define __CS_ALU_INSTR(opcode, op1, op2) CS_ALU_INSTR(CS_ALU_OPCODE_##opcode, \ argument
64 CS_ALU_OPERAND_##op2)
67 #define CS_ALU_INSTR_LOAD(op1, op2) __CS_ALU_INSTR(LOAD, op1, op2) argument
68 #define CS_ALU_INSTR_LOADINV(op1, op2) __CS_ALU_INSTR(LOADINV, op1, op2) argument
76 #define CS_ALU_INSTR_STORE(op1, op2) __CS_ALU_INSTR(STORE, op1, op2) argument
77 #define CS_ALU_INSTR_STOREINV(op1, op2) __CS_ALU_INSTR(STOREINV, op1, op2) argument
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| A D | phy_qmath.c | 13 u16 qm_mulu16(u16 op1, u16 op2) in qm_mulu16() argument
15 return (u16) (((u32) op1 * (u32) op2) >> 16); in qm_mulu16()
26 s16 qm_muls16(s16 op1, s16 op2) in qm_muls16() argument
32 result = ((s32) (op1) * (s32) (op2)); in qm_muls16()
42 s32 qm_add32(s32 op1, s32 op2) in qm_add32() argument
45 result = op1 + op2; in qm_add32()
46 if (op1 < 0 && op2 < 0 && result > 0) in qm_add32()
59 s16 qm_add16(s16 op1, s16 op2) in qm_add16() argument
62 s32 temp = (s32) op1 + (s32) op2; in qm_add16()
78 s16 qm_sub16(s16 op1, s16 op2) in qm_sub16() argument
[all …]
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| A D | phy_qmath.h | 11 u16 qm_mulu16(u16 op1, u16 op2);
13 s16 qm_muls16(s16 op1, s16 op2);
15 s32 qm_add32(s32 op1, s32 op2);
17 s16 qm_add16(s16 op1, s16 op2);
19 s16 qm_sub16(s16 op1, s16 op2);
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| /drivers/gpu/drm/i915/gt/ |
| A D | intel_gpu_commands.h | 345 #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) argument
348 #define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) argument
349 #define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) argument
357 #define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) argument
358 #define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) argument
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| /drivers/gpu/host1x/ |
| A D | cdma.c | 138 static void host1x_pushbuffer_push(struct push_buffer *pb, u32 op1, u32 op2) in host1x_pushbuffer_push() argument
144 *(p++) = op2; in host1x_pushbuffer_push()
590 void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2) in host1x_cdma_push() argument
597 op1, op2); in host1x_cdma_push()
605 host1x_pushbuffer_push(pb, op1, op2); in host1x_cdma_push()
617 void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2, in host1x_cdma_push_wide() argument
626 trace_host1x_cdma_push_wide(dev_name(channel->dev), op1, op2, in host1x_cdma_push_wide()
650 host1x_pushbuffer_push(pb, op1, op2); in host1x_cdma_push_wide()
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| A D | cdma.h | 83 void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2);
84 void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,
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| /drivers/gpu/host1x/hw/ |
| A D | channel_hw.c | 136 u32 op2, op3; in submit_gathers() local
138 op2 = lower_32_bits(addr); in submit_gathers()
148 host1x_cdma_push_wide(cdma, op1, op2, op3, op4); in submit_gathers()
157 host1x_cdma_push(cdma, op1, op2); in submit_gathers()
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| /drivers/iommu/ |
| A D | msm_iommu.c | 28 #define MRC(reg, processor, op1, crn, crm, op2) \ argument
30 " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
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