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Searched refs:opp_cnt (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c77 int opp_cnt = 1; in update_dsc_on_stream() local
81 opp_cnt++; in update_dsc_on_stream()
122 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
175 int opp_cnt = 0; in dcn314_update_odm() local
184 if (opp_cnt > 1) in dcn314_update_odm()
187 opp_inst, opp_cnt, in dcn314_update_odm()
194 for (i = 0; i < opp_cnt; ++i) { in dcn314_update_odm()
435 int opp_cnt = 1; in dcn314_resync_fifo_dccg_dio() local
442 opp_cnt++; in dcn314_resync_fifo_dccg_dio()
444 if (opp_cnt > 1) in dcn314_resync_fifo_dccg_dio()
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.c50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc314_set_odm_combine() argument
55 int h_active = segment_width * opp_cnt; in optc314_set_odm_combine()
64 if (opp_cnt == 4) { in optc314_set_odm_combine()
83 if (opp_cnt == 2) { in optc314_set_odm_combine()
88 } else if (opp_cnt == 4) { in optc314_set_odm_combine()
101 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc314_set_odm_combine()
102 optc1->opp_count = opp_cnt; in optc314_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/optc/dcn30/
A Ddcn30_optc.c218 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument
232 ASSERT(opp_cnt == 2 || opp_cnt == 4); in optc3_set_odm_combine()
237 if (opp_cnt == 2) { in optc3_set_odm_combine()
242 } else if (opp_cnt == 4) { in optc3_set_odm_combine()
253 if (opp_cnt == 2) { in optc3_set_odm_combine()
258 } else if (opp_cnt == 4) { in optc3_set_odm_combine()
270 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine()
271 optc1->opp_count = opp_cnt; in optc3_set_odm_combine()
A Ddcn30_optc.h360 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
/drivers/gpu/drm/amd/display/dc/optc/dcn32/
A Ddcn32_optc.c45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc32_set_odm_combine() argument
50 int h_active = segment_width * opp_cnt; in optc32_set_odm_combine()
59 if (opp_cnt == 4) { in optc32_set_odm_combine()
78 if (opp_cnt == 2) { in optc32_set_odm_combine()
83 } else if (opp_cnt == 4) { in optc32_set_odm_combine()
96 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
97 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.c57 static uint32_t decide_odm_mem_bit_map(int *opp_id, int opp_cnt, int h_active) in decide_odm_mem_bit_map() argument
66 for (i = 0; i < opp_cnt; i++) { in decide_odm_mem_bit_map()
74 for (i = 0; i < opp_cnt; i++) { in decide_odm_mem_bit_map()
105 int opp_cnt, int segment_width, int last_segment_width) in optc401_set_odm_combine() argument
108 uint32_t h_active = segment_width * (opp_cnt - 1) + last_segment_width; in optc401_set_odm_combine()
110 opp_id, opp_cnt, h_active); in optc401_set_odm_combine()
115 switch (opp_cnt) { in optc401_set_odm_combine()
162 optc1->opp_count = opp_cnt; in optc401_set_odm_combine()
A Ddcn401_optc.h190 int opp_cnt, int segment_width, int last_segment_width);
/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.c43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc31_set_odm_combine() argument
51 if (opp_cnt == 4) { in optc31_set_odm_combine()
71 if (opp_cnt == 2) { in optc31_set_odm_combine()
76 } else if (opp_cnt == 4) { in optc31_set_odm_combine()
88 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
89 optc1->opp_count = opp_cnt; in optc31_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/optc/dcn35/
A Ddcn35_optc.c58 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc35_set_odm_combine() argument
63 int h_active = segment_width * opp_cnt; in optc35_set_odm_combine()
72 if (opp_cnt == 4) { in optc35_set_odm_combine()
91 if (opp_cnt == 2) { in optc35_set_odm_combine()
96 } else if (opp_cnt == 4) { in optc35_set_odm_combine()
108 REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc35_set_odm_combine()
109 optc1->opp_count = opp_cnt; in optc35_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1017 int opp_cnt = 1; in dcn32_update_dsc_on_stream() local
1033 opp_cnt++; in dcn32_update_dsc_on_stream()
1132 int opp_cnt = 0; in dcn32_update_odm() local
1139 if (opp_cnt > 1) in dcn32_update_odm()
1142 opp_inst, opp_cnt, in dcn32_update_odm()
1278 int opp_cnt = 1; in dcn32_resync_fifo_dccg_dio() local
1285 opp_cnt++; in dcn32_resync_fifo_dccg_dio()
1287 if (opp_cnt > 1) in dcn32_resync_fifo_dccg_dio()
1290 opp_inst, opp_cnt, in dcn32_resync_fifo_dccg_dio()
1309 params.opp_cnt = 1; in dcn32_unblank_stream()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c322 int opp_cnt = 1; in update_dsc_on_stream() local
328 opp_cnt++; in update_dsc_on_stream()
355 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
356 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
367 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream()
368 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
421 int opp_cnt = 0; in dcn35_update_odm() local
428 opp_cnt = get_odm_config(pipe_ctx, opp_inst); in dcn35_update_odm()
430 if (opp_cnt > 1) in dcn35_update_odm()
433 opp_inst, opp_cnt, in dcn35_update_odm()
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
187 ASSERT(opp_cnt == 2); in optc2_set_odm_combine()
217 optc1->opp_count = opp_cnt; in optc2_set_odm_combine()
A Ddcn20_optc.h112 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c775 if (opp_cnt >= 2) in calc_mpc_flow_ctrl_cnt()
786 if (opp_cnt == 4) in calc_mpc_flow_ctrl_cnt()
832 int opp_cnt = 1; in dcn20_enable_stream_timing() local
862 for (i = 0; i < opp_cnt; i++) in dcn20_enable_stream_timing()
867 if (opp_cnt > 1) in dcn20_enable_stream_timing()
1186 int opp_cnt = 1; in dcn20_update_odm() local
1193 opp_cnt++; in dcn20_update_odm()
1196 if (opp_cnt > 1) in dcn20_update_odm()
1199 opp_inst, opp_cnt, in dcn20_update_odm()
2762 params.opp_cnt = 1; in dcn20_unblank_stream()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1221 int opp_cnt = 1; in get_pixel_clock_parameters() local
1228 opp_cnt++; in get_pixel_clock_parameters()
1252 if (opp_cnt == 4) in get_pixel_clock_parameters()
1254 …else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt =… in get_pixel_clock_parameters()
1268 opp_cnt > 1) { in get_pixel_clock_parameters()
1653 int opp_cnt = 1; in dcn20_validate_dsc() local
1656 opp_cnt++; in dcn20_validate_dsc()
1663 + stream->timing.h_border_right) / opp_cnt; in dcn20_validate_dsc()
1670 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn20_validate_dsc()
/drivers/gpu/drm/amd/display/dc/link/
A Dlink_dpms.c811 int opp_cnt = 1; in link_set_dsc_on_stream() local
827 opp_cnt++; in link_set_dsc_on_stream()
836 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in link_set_dsc_on_stream()
842 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in link_set_dsc_on_stream()
843 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in link_set_dsc_on_stream()
857 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in link_set_dsc_on_stream()
858 dsc_cfg.pic_width *= opp_cnt; in link_set_dsc_on_stream()
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c712 int *opp_cnt, in enable_stream_timing_calc() argument
724 *opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads); in enable_stream_timing_calc()
725 for (i = 0; i < *opp_cnt; i++) in enable_stream_timing_calc()
755 int opp_cnt = 1; in dcn401_enable_stream_timing() local
770 &opp_cnt, opp_heads, &manual_mode, &params, &event_triggers); in dcn401_enable_stream_timing()
780 if (opp_cnt > 1) { in dcn401_enable_stream_timing()
785 opp_inst, opp_cnt, in dcn401_enable_stream_timing()
828 for (i = 0; i < opp_cnt; i++) { in dcn401_enable_stream_timing()
1602 params.opp_cnt = resource_get_odm_slice_count(pipe_ctx); in dcn401_unblank_stream()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dstream_encoder.h101 int opp_cnt; member
A Dtiming_generator.h349 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.c312 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) { in enc314_stream_encoder_dp_unblank()
/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.c291 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1 in enc35_stream_encoder_dp_unblank()
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.c259 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1 in enc32_stream_encoder_dp_unblank()
/drivers/gpu/drm/amd/display/dc/dio/dcn20/
A Ddcn20_stream_encoder.c482 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) { in enc2_stream_encoder_dp_unblank()

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