| /drivers/soc/mediatek/ |
| A D | mtk-dvfsrc.c | 51 const struct dvfsrc_opp *opps; member
127 return &dvfsrc->curr_opps->opps[level]; in dvfsrc_get_current_opp()
152 target = &dvfsrc->curr_opps->opps[level]; in dvfsrc_wait_for_opp_level_v1()
172 target = &dvfsrc->curr_opps->opps[level]; in dvfsrc_wait_for_opp_level_v2()
307 const struct dvfsrc_opp *opp = &dvfsrc->curr_opps->opps[level]; in dvfsrc_set_opp_level_v1()
467 .opps = dvfsrc_opp_mt6893_lp4,
499 .opps = dvfsrc_opp_mt8183_lp4,
503 .opps = dvfsrc_opp_mt8183_lp3,
507 .opps = dvfsrc_opp_mt8183_lp3,
537 .opps = dvfsrc_opp_mt8195_lp4,
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| /drivers/firmware/ |
| A D | arm_scpi.c | 310 } opps[MAX_DVFS_OPPS]; member
643 info->opps = kcalloc(info->count, sizeof(*opp), GFP_KERNEL); in scpi_dvfs_get_info()
644 if (!info->opps) { in scpi_dvfs_get_info()
649 for (i = 0, opp = info->opps; i < info->count; i++, opp++) { in scpi_dvfs_get_info()
650 opp->freq = le32_to_cpu(buf.opps[i].freq); in scpi_dvfs_get_info()
651 opp->m_volt = le32_to_cpu(buf.opps[i].m_volt); in scpi_dvfs_get_info()
654 sort(info->opps, info->count, sizeof(*opp), opp_cmp_func, NULL); in scpi_dvfs_get_info()
700 if (!info->opps) in scpi_dvfs_add_opps_to_device()
703 for (opp = info->opps, idx = 0; idx < info->count; idx++, opp++) { in scpi_dvfs_add_opps_to_device()
877 kfree(info->dvfs[i]->opps); in scpi_remove()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 187 opp = dc->res_pool->opps[opp_id_src0]; in dcn201_init_blank()
298 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn201_init_hw()
299 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; in dcn201_init_hw()
301 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; in dcn201_init_hw()
323 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_init_hw()
324 pipe_ctx->stream_res.opp = res_pool->opps[i]; in dcn201_init_hw()
|
| /drivers/clk/ |
| A D | clk-scpi.c | 66 const struct scpi_opp *opp = clk->info->opps; in __scpi_dvfs_round_rate()
91 opp = clk->info->opps + idx; in scpi_dvfs_recalc_rate()
106 const struct scpi_opp *opp = clk->info->opps; in __scpi_find_dvfs_index()
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| /drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| A D | dce60_resource.c | 802 if (pool->base.opps[i] != NULL) in dce60_resource_destruct()
803 dce110_opp_destroy(&pool->base.opps[i]); in dce60_resource_destruct()
1068 pool->base.opps[i] = dce60_opp_create(ctx, i); in dce60_construct()
1069 if (pool->base.opps[i] == NULL) { in dce60_construct()
1266 pool->base.opps[i] = dce60_opp_create(ctx, i); in dce61_construct()
1267 if (pool->base.opps[i] == NULL) { in dce61_construct()
1463 pool->base.opps[i] = dce60_opp_create(ctx, i); in dce64_construct()
1464 if (pool->base.opps[i] == NULL) { in dce64_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| A D | dce80_resource.c | 808 if (pool->base.opps[i] != NULL) in dce80_resource_destruct()
809 dce110_opp_destroy(&pool->base.opps[i]); in dce80_resource_destruct()
1078 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce80_construct()
1079 if (pool->base.opps[i] == NULL) { in dce80_construct()
1278 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce81_construct()
1279 if (pool->base.opps[i] == NULL) { in dce81_construct()
1475 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce83_construct()
1476 if (pool->base.opps[i] == NULL) { in dce83_construct()
|
| /drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| A D | dcn35_hwseq.c | 812 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn35_init_pipes()
813 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; in dcn35_init_pipes()
814 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn35_init_pipes()
815 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; in dcn35_init_pipes()
838 if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) { in dcn35_init_pipes()
839 if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) { in dcn35_init_pipes()
840 int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id; in dcn35_init_pipes()
843 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; in dcn35_init_pipes()
|
| /drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| A D | dce110_resource.c | 817 if (pool->base.opps[i] != NULL) in dce110_resource_destruct()
818 dce110_opp_destroy(&pool->base.opps[i]); in dce110_resource_destruct()
1141 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; in dce110_acquire_underlay()
1270 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1477 pool->base.opps[i] = dce110_opp_create(ctx, i); in dce110_resource_construct()
1478 if (pool->base.opps[i] == NULL) { in dce110_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 950 if (pool->base.opps[i] != NULL) in dcn201_resource_destruct()
951 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn201_resource_destruct()
1230 pool->base.opps[i] = dcn201_opp_create(ctx, i); in dcn201_resource_construct()
1231 if (pool->base.opps[i] == NULL) { in dcn201_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| A D | dce100_resource.c | 761 if (pool->base.opps[i] != NULL) in dce100_resource_destruct()
762 dce110_opp_destroy(&pool->base.opps[i]); in dce100_resource_destruct()
1116 pool->base.opps[i] = dce100_opp_create(ctx, i); in dce100_resource_construct()
1117 if (pool->base.opps[i] == NULL) { in dce100_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 1050 if (pool->opps[i] != NULL) in dcn302_resource_destruct()
1051 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); in dcn302_resource_destruct()
1388 pool->opps[i] = dcn302_opp_create(ctx, i); in dcn302_resource_construct()
1389 if (pool->opps[i] == NULL) { in dcn302_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 995 if (pool->opps[i] != NULL) in dcn303_resource_destruct()
996 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); in dcn303_resource_destruct()
1321 pool->opps[i] = dcn303_opp_create(ctx, i); in dcn303_resource_construct()
1322 if (pool->opps[i] == NULL) { in dcn303_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 920 if (pool->base.opps[i] != NULL) in dcn10_resource_destruct()
921 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn10_resource_destruct()
1591 pool->base.opps[j] = dcn10_opp_create(ctx, i); in dcn10_resource_construct()
1592 if (pool->base.opps[j] == NULL) { in dcn10_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| A D | dce120_resource.c | 602 if (pool->base.opps[i] != NULL) in dce120_resource_destruct()
603 dce110_opp_destroy(&pool->base.opps[i]); in dce120_resource_destruct()
1212 pool->base.opps[j] = dce120_opp_create( in dce120_resource_construct()
1215 if (pool->base.opps[j] == NULL) { in dce120_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 707 if (pool->base.opps[i] != NULL) in dcn21_resource_destruct()
708 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn21_resource_destruct()
1602 pool->base.opps[j] = dcn21_opp_create(ctx, i); in dcn21_resource_construct()
1603 if (pool->base.opps[j] == NULL) { in dcn21_resource_construct()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 1099 if (pool->base.opps[i] != NULL) in dcn301_destruct()
1100 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn301_destruct()
1613 pool->base.opps[j] = dcn301_opp_create(ctx, i); in dcn301_resource_construct()
1614 if (pool->base.opps[j] == NULL) { in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| A D | dce112_resource.c | 782 if (pool->base.opps[i] != NULL) in dce112_resource_destruct()
783 dce110_opp_destroy(&pool->base.opps[i]); in dce112_resource_destruct()
1364 pool->base.opps[i] = dce112_opp_create( in dce112_resource_construct()
1367 if (pool->base.opps[i] == NULL) { in dce112_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 1660 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { in dcn32_init_blank()
1661 opp = dc->res_pool->opps[i]; in dcn32_init_blank()
1674 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) { in dcn32_init_blank()
1675 bottom_opp = dc->res_pool->opps[i]; in dcn32_init_blank()
|
| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 609 if (pool->opps[i]->funcs->dpg_is_blanked) in dcn10_log_hw_state()
610 s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]); in dcn10_log_hw_state()
1644 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn10_init_pipes()
1645 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; in dcn10_init_pipes()
1646 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_init_pipes()
1647 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; in dcn10_init_pipes()
1670 if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) { in dcn10_init_pipes()
1671 if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) { in dcn10_init_pipes()
1672 int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id; in dcn10_init_pipes()
1675 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; in dcn10_init_pipes()
|
| /drivers/net/phy/ |
| A D | nxp-c45-tja11xx-macsec.c | 218 u16 opps; member
257 .opps = MACSEC_TXSA_A_OPPS,
268 .opps = MACSEC_TXSA_B_OPPS,
543 nxp_c45_macsec_write(phydev, sa->regs->opps, 0); in nxp_c45_tx_sa_clear_stats()
551 nxp_c45_macsec_read(phydev, sa->regs->opps, &stats->OutPktsProtected); in nxp_c45_tx_sa_read_stats()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 1425 if (pool->base.opps[i] != NULL) in dcn316_resource_destruct()
1426 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn316_resource_destruct()
1910 pool->base.opps[i] = dcn31_opp_create(ctx, i); in dcn316_resource_construct()
1911 if (pool->base.opps[i] == NULL) { in dcn316_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 1486 if (pool->base.opps[i] != NULL) in dcn314_resource_destruct()
1487 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn314_resource_destruct()
2009 pool->base.opps[i] = dcn31_opp_create(ctx, i); in dcn314_resource_construct()
2010 if (pool->base.opps[i] == NULL) { in dcn314_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 1128 if (pool->base.opps[i] != NULL) in dcn30_resource_destruct()
1129 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn30_resource_destruct()
1558 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
2487 pool->base.opps[i] = dcn30_opp_create(ctx, i); in dcn30_resource_construct()
2488 if (pool->base.opps[i] == NULL) { in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 1429 if (pool->base.opps[i] != NULL) in dcn31_resource_destruct()
1430 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn31_resource_destruct()
2086 pool->base.opps[i] = dcn31_opp_create(ctx, i); in dcn31_resource_construct()
2087 if (pool->base.opps[i] == NULL) { in dcn31_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 1415 if (pool->base.opps[i] != NULL) in dcn321_resource_destruct()
1416 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn321_resource_destruct()
1900 pool->base.opps[j] = dcn321_opp_create(ctx, i); in dcn321_resource_construct()
1901 if (pool->base.opps[j] == NULL) { in dcn321_resource_construct()
|