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Searched refs:optc1 (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/display/dc/optc/dcn201/
A Ddcn201_optc.c32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
103 if (h_blank < optc1->min_h_blank) in optc201_validate_timing()
110 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; in optc201_validate_timing()
190 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn201_timing_generator_init()
191 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn201_timing_generator_init()
193 optc1->min_h_blank = 32; in dcn201_timing_generator_init()
194 optc1->min_v_blank = 3; in dcn201_timing_generator_init()
196 optc1->min_h_sync_width = 8; in dcn201_timing_generator_init()
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/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c33 optc1->tg_regs->reg
36 optc1->base.ctx
40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
179 optc1->signal = signal; in optc1_program_timing()
320 if (optc1->opp_count == 4) in optc1_program_timing()
637 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; in optc1_validate_timing()
1675 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
1676 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn10_timing_generator_init()
1678 optc1->min_h_blank = 32; in dcn10_timing_generator_init()
1679 optc1->min_v_blank = 3; in dcn10_timing_generator_init()
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/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c31 optc1->tg_regs->reg
34 optc1->base.ctx
38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
178 optc1->opp_count = 1; in optc2_set_odm_bypass()
217 optc1->opp_count = opp_cnt; in optc2_set_odm_combine()
572 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
573 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn20_timing_generator_init()
575 optc1->min_h_blank = 32; in dcn20_timing_generator_init()
576 optc1->min_v_blank = 3; in dcn20_timing_generator_init()
577 optc1->min_v_blank_interlace = 5; in dcn20_timing_generator_init()
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn30/
A Ddcn30_optc.c36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
215 optc1->opp_count = 1; in optc3_set_odm_bypass()
271 optc1->opp_count = opp_cnt; in optc3_set_odm_combine()
430 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn30_timing_generator_init()
431 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn30_timing_generator_init()
433 optc1->min_h_blank = 32; in dcn30_timing_generator_init()
434 optc1->min_v_blank = 3; in dcn30_timing_generator_init()
436 optc1->min_h_sync_width = 4; in dcn30_timing_generator_init()
[all …]
A Ddcn30_optc.h330 void dcn30_timing_generator_init(struct optc *optc1);
/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.c15 optc1->tg_regs->reg
18 optc1->base.ctx
22 optc1->tg_shift->field_name, optc1->tg_mask->field_name
162 optc1->opp_count = opp_cnt; in optc401_set_odm_combine()
282 optc1->opp_count = 1; in optc401_set_odm_bypass()
537 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn401_timing_generator_init()
538 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn401_timing_generator_init()
540 optc1->min_h_blank = 32; in dcn401_timing_generator_init()
541 optc1->min_v_blank = 3; in dcn401_timing_generator_init()
543 optc1->min_h_sync_width = 4; in dcn401_timing_generator_init()
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A Ddcn401_optc.h169 void dcn401_timing_generator_init(struct optc *optc1);
/drivers/gpu/drm/amd/display/dc/optc/dcn32/
A Ddcn32_optc.c36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
97 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
247 optc1->opp_count = 1; in optc32_set_odm_bypass()
374 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn32_timing_generator_init()
375 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn32_timing_generator_init()
377 optc1->min_h_blank = 32; in dcn32_timing_generator_init()
378 optc1->min_v_blank = 3; in dcn32_timing_generator_init()
380 optc1->min_h_sync_width = 4; in dcn32_timing_generator_init()
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A Ddcn32_optc.h187 void dcn32_timing_generator_init(struct optc *optc1);
/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.c36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
102 optc1->opp_count = opp_cnt; in optc314_set_odm_combine()
183 optc1->opp_count = 1; in optc314_set_odm_bypass()
265 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn314_timing_generator_init()
266 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn314_timing_generator_init()
268 optc1->min_h_blank = 32; in dcn314_timing_generator_init()
269 optc1->min_v_blank = 3; in dcn314_timing_generator_init()
271 optc1->min_h_sync_width = 4; in dcn314_timing_generator_init()
[all …]
A Ddcn314_optc.h260 void dcn314_timing_generator_init(struct optc *optc1);
/drivers/gpu/drm/amd/display/dc/optc/dcn35/
A Ddcn35_optc.c38 optc1->tg_regs->reg
41 optc1->base.ctx
45 optc1->tg_shift->field_name, optc1->tg_mask->field_name
109 optc1->opp_count = opp_cnt; in optc35_set_odm_combine()
219 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) in optc35_configure_crc()
252 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) in optc35_configure_crc()
502 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn35_timing_generator_init()
503 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn35_timing_generator_init()
505 optc1->min_h_blank = 32; in dcn35_timing_generator_init()
506 optc1->min_v_blank = 3; in dcn35_timing_generator_init()
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A Ddcn35_optc.h77 void dcn35_timing_generator_init(struct optc *optc1);
79 void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);
/drivers/gpu/drm/amd/display/dc/optc/dcn301/
A Ddcn301_optc.c36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
180 optc1->base.funcs = &dcn30_tg_funcs; in dcn301_timing_generator_init()
182 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn301_timing_generator_init()
183 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn301_timing_generator_init()
185 optc1->min_h_blank = 32; in dcn301_timing_generator_init()
186 optc1->min_v_blank = 3; in dcn301_timing_generator_init()
187 optc1->min_v_blank_interlace = 5; in dcn301_timing_generator_init()
188 optc1->min_h_sync_width = 4; in dcn301_timing_generator_init()
[all …]
A Ddcn301_optc.h32 void dcn301_timing_generator_init(struct optc *optc1);
/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.c34 optc1->tg_regs->reg
37 optc1->base.ctx
41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
89 optc1->opp_count = opp_cnt; in optc31_set_odm_combine()
245 optc1->opp_count = 1; in optc3_init_odm()
386 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
387 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn31_timing_generator_init()
389 optc1->min_h_blank = 32; in dcn31_timing_generator_init()
390 optc1->min_v_blank = 3; in dcn31_timing_generator_init()
392 optc1->min_h_sync_width = 4; in dcn31_timing_generator_init()
[all …]
A Ddcn31_optc.h266 void dcn31_timing_generator_init(struct optc *optc1);
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c37 optc1->tg_regs->reg
40 optc1->base.ctx
44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c196 struct optc *optc1 = DCN10TG_FROM_TG(tg); in dcn10_set_wait_for_update_needed_for_pipe() local
198 ASSERT(optc1->max_frame_count != 0); in dcn10_set_wait_for_update_needed_for_pipe()
210 if (cur_frame + 1 > optc1->max_frame_count) in dcn10_set_wait_for_update_needed_for_pipe()
211 pipe_ctx->wait_frame_count = cur_frame + 1 - optc1->max_frame_count; in dcn10_set_wait_for_update_needed_for_pipe()

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