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Searched refs:optimal (Results 1 – 9 of 9) sorted by relevance

/drivers/cpufreq/
A Dfreq_table.c143 optimal.frequency = ~0; in cpufreq_table_index_unsorted()
153 optimal.driver_data = i; in cpufreq_table_index_unsorted()
160 optimal.frequency = freq; in cpufreq_table_index_unsorted()
161 optimal.driver_data = i; in cpufreq_table_index_unsorted()
173 optimal.frequency = freq; in cpufreq_table_index_unsorted()
174 optimal.driver_data = i; in cpufreq_table_index_unsorted()
185 if (diff < optimal.frequency || in cpufreq_table_index_unsorted()
188 optimal.frequency = diff; in cpufreq_table_index_unsorted()
189 optimal.driver_data = i; in cpufreq_table_index_unsorted()
194 if (optimal.driver_data > i) { in cpufreq_table_index_unsorted()
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/drivers/net/wireless/ath/ath12k/
A DKconfig34 you want optimal performance choose N.
43 you want optimal performance choose N.
52 you want optimal performance choose N.
/drivers/gpu/drm/i915/display/
A Di9xx_wm.c1287 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm() local
1293 *intermediate = *optimal; in g4x_compute_intermediate_wm()
1308 max(optimal->wm.plane[plane_id], in g4x_compute_intermediate_wm()
1959 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal; in vlv_compute_intermediate_wm() local
1965 *intermediate = *optimal; in vlv_compute_intermediate_wm()
2928 pipe_wm = &crtc_state->wm.ilk.optimal; in ilk_compute_pipe_wm()
2996 const struct intel_pipe_wm *optimal = &new_crtc_state->wm.ilk.optimal; in ilk_compute_intermediate_wm() local
3005 *intermediate = *optimal; in ilk_compute_intermediate_wm()
3829 crtc_state->wm.g4x.optimal = *active; in g4x_wm_get_hw_state()
3891 crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
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A Dskl_watermark.c321 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
343 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
366 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
1511 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1577 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
2728 old_pipe_wm = &old_crtc_state->wm.skl.optimal; in skl_print_wm_changes()
2729 new_pipe_wm = &new_crtc_state->wm.skl.optimal; in skl_print_wm_changes()
2839 &old_crtc_state->wm.skl.optimal, in skl_wm_add_affected_planes()
2840 &new_crtc_state->wm.skl.optimal)) in skl_wm_add_affected_planes()
3073 memset(&crtc_state->wm.skl.optimal, 0, in skl_wm_get_hw_state()
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A Dintel_display_types.h876 struct intel_pipe_wm optimal; member
882 struct skl_pipe_wm optimal; member
903 struct vlv_wm_state optimal; /* inverted */ member
910 struct g4x_wm_state optimal; member
A Dintel_cursor.c633 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_cursor_wm()
A Dskl_universal_plane.c833 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_plane_wm()
/drivers/devfreq/
A DKconfig91 This does not yet operate with optimal voltages.
/drivers/infiniband/ulp/rtrs/
A DREADME6 which provides support to establish optimal number of connections

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