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Searched refs:oq_no (Results 1 – 12 of 12) sorted by relevance

/drivers/net/ethernet/marvell/octeon_ep_vf/
A Doctep_vf_cnxk.c204 struct octep_vf_oq *oq = oct->oq[oq_no]; in octep_vf_setup_oq_regs_cnxk()
209 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); in octep_vf_setup_oq_regs_cnxk()
229 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no), reg_val); in octep_vf_setup_oq_regs_cnxk()
233 oq_ctl = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); in octep_vf_setup_oq_regs_cnxk()
238 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no), oq_ctl); in octep_vf_setup_oq_regs_cnxk()
249 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no)); in octep_vf_setup_oq_regs_cnxk()
252 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), reg_val); in octep_vf_setup_oq_regs_cnxk()
409 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no)); in octep_vf_enable_oq_cnxk()
411 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no), reg_val); in octep_vf_enable_oq_cnxk()
440 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no)); in octep_vf_disable_oq_cnxk()
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A Doctep_vf_cn9k.c201 struct octep_vf_oq *oq = oct->oq[oq_no]; in octep_vf_setup_oq_regs_cn93()
206 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_CONTROL(oq_no)); in octep_vf_setup_oq_regs_cn93()
211 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_CONTROL(oq_no)); in octep_vf_setup_oq_regs_cn93()
226 octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_CONTROL(oq_no), reg_val); in octep_vf_setup_oq_regs_cn93()
230 oq_ctl = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_CONTROL(oq_no)); in octep_vf_setup_oq_regs_cn93()
233 octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_CONTROL(oq_no), oq_ctl); in octep_vf_setup_oq_regs_cn93()
236 oq->pkts_sent_reg = oct->mmio.hw_addr + CN93_VF_SDP_R_OUT_CNTS(oq_no); in octep_vf_setup_oq_regs_cn93()
398 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_ENABLE(oq_no)); in octep_vf_enable_oq_cn93()
400 octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_ENABLE(oq_no), reg_val); in octep_vf_enable_oq_cn93()
429 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_OUT_ENABLE(oq_no)); in octep_vf_disable_oq_cn93()
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/drivers/net/ethernet/marvell/octeon_ep/
A Doctep_cnxk_pf.c335 struct octep_oq *oq = oct->oq[oq_no]; in octep_setup_oq_regs_cnxk_pf()
337 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); in octep_setup_oq_regs_cnxk_pf()
359 octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), in octep_setup_oq_regs_cnxk_pf()
361 octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), in octep_setup_oq_regs_cnxk_pf()
364 oq_ctl = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); in octep_setup_oq_regs_cnxk_pf()
371 octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), oq_ctl); in octep_setup_oq_regs_cnxk_pf()
376 CNXK_SDP_R_OUT_SLIST_DBELL(oq_no); in octep_setup_oq_regs_cnxk_pf()
384 reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no)); in octep_setup_oq_regs_cnxk_pf()
387 octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), reg_val); in octep_setup_oq_regs_cnxk_pf()
790 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); in octep_enable_oq_cnxk_pf()
[all …]
A Doctep_cn9k_pf.c315 struct octep_oq *oq = oct->oq[oq_no]; in octep_setup_oq_regs_cn93_pf()
317 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); in octep_setup_oq_regs_cn93_pf()
318 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no)); in octep_setup_oq_regs_cn93_pf()
338 octep_write_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no), reg_val); in octep_setup_oq_regs_cn93_pf()
339 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_BADDR(oq_no), in octep_setup_oq_regs_cn93_pf()
341 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_RSIZE(oq_no), in octep_setup_oq_regs_cn93_pf()
344 oq_ctl = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no)); in octep_setup_oq_regs_cn93_pf()
347 octep_write_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no), oq_ctl); in octep_setup_oq_regs_cn93_pf()
352 CN93_SDP_R_OUT_SLIST_DBELL(oq_no); in octep_setup_oq_regs_cn93_pf()
767 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); in octep_enable_oq_cn93_pf()
[all …]
/drivers/net/ethernet/cavium/liquidio/
A Dcn66xx_device.c304 struct octeon_droq *droq = oct->droq[oq_no]; in lio_cn6xxx_setup_oq_regs()
315 oct->mmio[0].hw_addr + CN6XXX_SLI_OQ_PKTS_SENT(oq_no); in lio_cn6xxx_setup_oq_regs()
321 intr |= (1 << oq_no); in lio_cn6xxx_setup_oq_regs()
326 intr |= (1 << oq_no); in lio_cn6xxx_setup_oq_regs()
509 int oq_no; in lio_cn6xxx_process_droq_intr_regs() local
525 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct); oq_no++) { in lio_cn6xxx_process_droq_intr_regs()
526 if (!(droq_mask & BIT_ULL(oq_no))) in lio_cn6xxx_process_droq_intr_regs()
529 droq = oct->droq[oq_no]; in lio_cn6xxx_process_droq_intr_regs()
532 oct->droq_intr |= BIT_ULL(oq_no); in lio_cn6xxx_process_droq_intr_regs()
545 value &= ~(1 << oq_no); in lio_cn6xxx_process_droq_intr_regs()
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A Dcn23xx_pf_device.c462 struct octeon_droq *droq = oct->droq[oq_no]; in cn23xx_setup_oq_regs()
467 oq_no += oct->sriov_info.pf_srn; in cn23xx_setup_oq_regs()
469 octeon_write_csr64(oct, CN23XX_SLI_OQ_BASE_ADDR64(oq_no), in cn23xx_setup_oq_regs()
471 octeon_write_csr(oct, CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count); in cn23xx_setup_oq_regs()
473 octeon_write_csr(oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no), in cn23xx_setup_oq_regs()
478 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_PKTS_SENT(oq_no); in cn23xx_setup_oq_regs()
486 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
488 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no), in cn23xx_setup_oq_regs()
494 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
496 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no), in cn23xx_setup_oq_regs()
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A Dcn23xx_vf_device.c245 static void cn23xx_setup_vf_oq_regs(struct octeon_device *oct, u32 oq_no) in cn23xx_setup_vf_oq_regs() argument
247 struct octeon_droq *droq = oct->droq[oq_no]; in cn23xx_setup_vf_oq_regs()
249 octeon_write_csr64(oct, CN23XX_VF_SLI_OQ_BASE_ADDR64(oq_no), in cn23xx_setup_vf_oq_regs()
251 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_SIZE(oq_no), droq->max_count); in cn23xx_setup_vf_oq_regs()
253 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq_no), in cn23xx_setup_vf_oq_regs()
258 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_SENT(oq_no); in cn23xx_setup_vf_oq_regs()
260 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq_no); in cn23xx_setup_vf_oq_regs()
A Dcn66xx_device.h77 void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no);
A Dlio_core.c964 u64 oq_no; in liquidio_schedule_droq_pkt_handlers() local
967 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct); in liquidio_schedule_droq_pkt_handlers()
968 oq_no++) { in liquidio_schedule_droq_pkt_handlers()
969 if (!(oct->droq_intr & BIT_ULL(oq_no))) in liquidio_schedule_droq_pkt_handlers()
972 droq = oct->droq[oq_no]; in liquidio_schedule_droq_pkt_handlers()
976 oct_priv->napi_mask |= BIT_ULL(oq_no); in liquidio_schedule_droq_pkt_handlers()
A Docteon_device.c921 u32 oq_no = 0; in octeon_setup_output_queues() local
943 if (octeon_init_droq(oct, oq_no, num_descs, desc_size, NULL)) { in octeon_setup_output_queues()
944 vfree(oct->droq[oq_no]); in octeon_setup_output_queues()
945 oct->droq[oq_no] = NULL; in octeon_setup_output_queues()
A Dlio_vf_main.c1180 int i, iq_no, oq_no; in liquidio_get_stats64() local
1204 oq_no = lio->linfo.rxpciq[i].s.q_no; in liquidio_get_stats64()
1205 oq_stats = &oct->droq[oq_no]->stats; in liquidio_get_stats64()
A Dlio_main.c2045 int i, iq_no, oq_no; in liquidio_get_stats64() local
2069 oq_no = lio->linfo.rxpciq[i].s.q_no; in liquidio_get_stats64()
2070 oq_stats = &oct->droq[oq_no]->stats; in liquidio_get_stats64()

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